src/soc/intel/meteorlake/finalize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <bootstate.h>
   5 #include <console/console.h>
   6 #include <cpu/x86/smm.h>
   7 #include <device/pci.h>
   8 #include <gpio.h>
   9 #include <intelblocks/cse.h>
  10 #include <intelblocks/lpc_lib.h>
  11 #include <intelblocks/pcr.h>
  12 #include <intelblocks/pmclib.h>
  13 #include <intelblocks/systemagent.h>
  14 #include <intelblocks/tco.h>
  15 #include <intelblocks/thermal.h>
  16 #include <spi-generic.h>
  17 #include <intelpch/lockdown.h>
  18 #include <soc/p2sb.h>
  19 #include <soc/pci_devs.h>
  20 #include <soc/pcr_ids.h>
  21 #include <soc/pm.h>
  22 #include <soc/smbus.h>
  23 #include <soc/soc_chip.h>
  24 #include <soc/systemagent.h>
  25
  26 static void pch_finalize(void)
  27 {
  28         /* TCO Lock down */
  29         tco_lockdown();
  30
  31         /* TODO: Add Thermal Configuration */
  32
  33         pmc_clear_pmcon_sts();
  34 }
  35
  36 static void tbt_finalize(void)
  37 {
  38         int i;
  39         const struct device *dev;
  40
  41         /* Disable Thunderbolt PCIe root ports bus master */
  42         for (i = 0; i < NUM_TBT_FUNCTIONS; i++) {
  43                 dev = pcidev_path_on_root(PCI_DEVFN_TBT(i));
  44                 if (dev)
  45                         pci_dev_disable_bus_master(dev);
  46         }
  47 }
  48
  49 static void sa_finalize(void)
  50 {
  51         if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT)
  52                 sa_lock_pam();
  53 }
  54
  55 static void heci_finalize(void)
  56 {
  57         heci_set_to_d0i3();
  58         if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
  59                 heci1_disable();
  60 }
  61
  62 static void soc_finalize(void *unused)
  63 {
  64         printk(BIOS_DEBUG, "Finalizing chipset.\n");
  65
  66         pch_finalize();
  67         apm_control(APM_CNT_FINALIZE);
  68         tbt_finalize();
  69         sa_finalize();
  70         if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) &&
  71                          CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
  72                 heci_finalize();
  73
  74         /* Indicate finalize step with post code */
  75         post_code(POSTCODE_OS_BOOT);
  76 }
  77
  78 BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
  79 /*
  80  * The purpose of this change is to accommodate more time to push out sending
  81  * CSE EOP messages at post.
  82  */
  83 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, soc_finalize, NULL);