src/soc/intel/meteorlake/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <gpio.h>
   4 #include <intelblocks/pcr.h>
   5 #include <soc/pcr_ids.h>
   6 #include <soc/pmc.h>
   7
   8 #define DEFAULT_VW_BASE         0x10
   9
  10 static const struct reset_mapping rst_map[] = {
  11         { .logical = PAD_RESET(PWROK), .chipset = 0U << 30 },
  12         { .logical = PAD_RESET(DEEP), .chipset = 1U << 30 },
  13         { .logical = PAD_RESET(PLTRST), .chipset = 2U << 30 },
  14         { .logical = PAD_RESET(GLBRST), .chipset = 3U << 30 },
  15 };
  16
  17 /*
  18  * The GPIO pinctrl driver for Meteor Lake on Linux expects 32 GPIOs per pad
  19  * group, regardless of whether or not there is a physical pad for each
  20  * exposed GPIO number.
  21  *
  22  * This results in the OS having a sparse GPIO map, and devices that need
  23  * to export an ACPI GPIO must use the OS expected number.
  24  *
  25  * Not all pins are usable as GPIO and those groups do not have a pad base.
  26  */
  27 static const struct pad_group mtl_community0_groups[] = {
  28         INTEL_GPP(GPP_PECI, GPP_PECI, GPP_VIDALERT_B),                  /* GPP_CPU */
  29         INTEL_GPP_BASE(GPP_PECI, GPP_V00, GPP_V23, 32),                 /* GPP_V */
  30         INTEL_GPP_BASE(GPP_PECI, GPP_C00, GPP_C23, 64),                 /* GPP_C */
  31 };
  32
  33 static const struct vw_entries mtl_community0_vw[] = {
  34         {GPP_C00, GPP_C23},
  35 };
  36
  37 static const struct pad_group mtl_community1_groups[] = {
  38         INTEL_GPP_BASE(GPP_A00, GPP_A00, GPP_ESPI_CLK_LPBK, 96),        /* GPP_A */
  39         INTEL_GPP_BASE(GPP_A00, GPP_E00, GPP_THC0_GSPI_CLK_LPBK, 128),  /* GPP_E */
  40 };
  41
  42 static const struct vw_entries mtl_community1_vw[] = {
  43         {GPP_A00, GPP_A20},
  44         {GPP_E00, GPP_E23},
  45 };
  46
  47 static const struct pad_group mtl_community3_groups[] = {
  48         INTEL_GPP_BASE(GPP_H00, GPP_H00, GPP_LPI3C0_CLK_LPBK, 160),     /* GPP_H */
  49         INTEL_GPP_BASE(GPP_H00, GPP_F00, GPP_GSPI0A_CLK_LOOPBK, 192),   /* GPP_F */
  50         INTEL_GPP(GPP_H00, GPP_SPI0_IO_2, GPP_SPI0_CLK_LOOPBK),         /* GPP_SPI0 */
  51         INTEL_GPP(GPP_H00, GPP_VGPIO3_USB0, GPP_VGPIO3_THC3),           /* GPP_VGPIO3 */
  52 };
  53
  54 static const struct vw_entries mtl_community3_vw[] = {
  55         {GPP_H00, GPP_H23},
  56         {GPP_F00, GPP_F23},
  57 };
  58
  59 static const struct pad_group mtl_community4_groups[] = {
  60         INTEL_GPP_BASE(GPP_S00, GPP_S00, GPP_S07, 288),                 /* GPP_S */
  61         INTEL_GPP(GPP_S00, GPP_JTAG_MBPB0, GPP_JTAG_TRST_B),            /* GPP_JTAG */
  62 };
  63
  64 static const struct pad_group mtl_community5_groups[] = {
  65         INTEL_GPP_BASE(GPP_B00, GPP_B00, GPP_ACI3C0_CLK_LPBK, 352),     /* GPP_B */
  66         INTEL_GPP_BASE(GPP_B00, GPP_D00, GPP_BOOTHALT_B, 384),          /* GPP_D */
  67         INTEL_GPP(GPP_B00, GPP_VGPIO00, GPP_VGPIO47),                   /* GPP_VGPIO */
  68 };
  69
  70 static const struct vw_entries mtl_community5_vw[] = {
  71         {GPP_B00, GPP_B23},
  72         {GPP_D00, GPP_D23},
  73 };
  74
  75 static const struct pad_community mtl_communities[] = {
  76         [COMM_0] = { /* GPP CPU, V, C */
  77                 .port = PID_GPIOCOM0,
  78                 .cpu_port = PID_GPIOCOM0,
  79                 .first_pad = GPIO_COM0_START,
  80                 .last_pad = GPIO_COM0_END,
  81                 .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
  82                 .pad_cfg_base = PAD_CFG_BASE,
  83                 .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET,
  84                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
  85                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
  86                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
  87                 .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
  88                 .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
  89                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
  90                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
  91                 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
  92                 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
  93                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
  94                 .name = "GPP_CPUVC",
  95                 .acpi_path = "\\_SB.PCI0.GPIO",
  96                 .reset_map = rst_map,
  97                 .num_reset_vals = ARRAY_SIZE(rst_map),
  98                 .groups = mtl_community0_groups,
  99                 .num_groups = ARRAY_SIZE(mtl_community0_groups),
 100                 .vw_base = DEFAULT_VW_BASE,
 101                 .vw_entries = mtl_community0_vw,
 102                 .num_vw_entries = ARRAY_SIZE(mtl_community0_vw),
 103         },
 104         [COMM_1] = { /* GPP A, E */
 105                 .port = PID_GPIOCOM1,
 106                 .cpu_port = PID_GPIOCOM1,
 107                 .first_pad = GPIO_COM1_START,
 108                 .last_pad = GPIO_COM1_END,
 109                 .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
 110                 .pad_cfg_base = PAD_CFG_BASE,
 111                 .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET,
 112                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 113                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 114                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 115                 .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
 116                 .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 117                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 118                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 119                 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
 120                 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
 121                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 122                 .name = "GPP_AE",
 123                 .acpi_path = "\\_SB.PCI0.GPIO",
 124                 .reset_map = rst_map,
 125                 .num_reset_vals = ARRAY_SIZE(rst_map),
 126                 .groups = mtl_community1_groups,
 127                 .num_groups = ARRAY_SIZE(mtl_community1_groups),
 128                 .vw_base = DEFAULT_VW_BASE,
 129                 .vw_entries = mtl_community1_vw,
 130                 .num_vw_entries = ARRAY_SIZE(mtl_community1_vw),
 131         },
 132         [COMM_3] = { /* GPP H, F, SPI0, VGPIO3 */
 133                 .port = PID_GPIOCOM3,
 134                 .cpu_port = PID_GPIOCOM3,
 135                 .first_pad = GPIO_COM3_START,
 136                 .last_pad = GPIO_COM3_END,
 137                 .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
 138                 .pad_cfg_base = PAD_CFG_BASE,
 139                 .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET,
 140                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 141                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 142                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 143                 .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
 144                 .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 145                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 146                 .name = "GPP_HFSPI0VG3",
 147                 .acpi_path = "\\_SB.PCI0.GPIO",
 148                 .reset_map = rst_map,
 149                 .num_reset_vals = ARRAY_SIZE(rst_map),
 150                 .groups = mtl_community3_groups,
 151                 .num_groups = ARRAY_SIZE(mtl_community3_groups),
 152                 .vw_base = DEFAULT_VW_BASE,
 153                 .vw_entries = mtl_community3_vw,
 154                 .num_vw_entries = ARRAY_SIZE(mtl_community3_vw),
 155         },
 156         [COMM_4] = { /* GPP S, JTAG */
 157                 .port = PID_GPIOCOM4,
 158                 .cpu_port = PID_GPIOCOM4,
 159                 .first_pad = GPIO_COM4_START,
 160                 .last_pad = GPIO_COM4_END,
 161                 .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
 162                 .pad_cfg_base = PAD_CFG_BASE,
 163                 .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET,
 164                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 165                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 166                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 167                 .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
 168                 .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 169                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 170                 .name = "GPP_SJTAG",
 171                 .acpi_path = "\\_SB.PCI0.GPIO",
 172                 .reset_map = rst_map,
 173                 .num_reset_vals = ARRAY_SIZE(rst_map),
 174                 .groups = mtl_community4_groups,
 175                 .num_groups = ARRAY_SIZE(mtl_community4_groups),
 176         },
 177         [COMM_5] = { /* GPP B, D, VGPIO */
 178                 .port = PID_GPIOCOM5,
 179                 .cpu_port = PID_GPIOCOM5,
 180                 .first_pad = GPIO_COM5_START,
 181                 .last_pad = GPIO_COM5_END,
 182                 .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
 183                 .pad_cfg_base = PAD_CFG_BASE,
 184                 .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET,
 185                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 186                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 187                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 188                 .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
 189                 .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 190                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 191                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 192                 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
 193                 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
 194                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 195                 .name = "GPP_BDVG",
 196                 .acpi_path = "\\_SB.PCI0.GPIO",
 197                 .reset_map = rst_map,
 198                 .num_reset_vals = ARRAY_SIZE(rst_map),
 199                 .groups = mtl_community5_groups,
 200                 .num_groups = ARRAY_SIZE(mtl_community5_groups),
 201                 .vw_base = DEFAULT_VW_BASE,
 202                 .vw_entries = mtl_community5_vw,
 203                 .num_vw_entries = ARRAY_SIZE(mtl_community5_vw),
 204         }
 205 };
 206
 207 const struct pad_community *soc_gpio_get_community(size_t *num_communities)
 208 {
 209         *num_communities = ARRAY_SIZE(mtl_communities);
 210         return mtl_communities;
 211 }
 212
 213 const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
 214 {
 215         static const struct pmc_to_gpio_route routes[] = {
 216                 { PMC_GPP_V, GPP_V },
 217                 { PMC_GPP_C, GPP_C },
 218                 { PMC_GPP_A, GPP_A },
 219                 { PMC_GPP_E, GPP_E },
 220                 { PMC_GPP_H, GPP_H },
 221                 { PMC_GPP_F, GPP_F },
 222                 { PMC_GPP_VGPIO3, GPP_VGPIO3 },
 223                 { PMC_GPP_VGPIO, GPP_VGPIO },
 224                 { PMC_GPP_S, GPP_S },
 225                 { PMC_GPP_B, GPP_B },
 226                 { PMC_GPP_D, GPP_D },
 227         };
 228         *num = ARRAY_SIZE(routes);
 229         return routes;
 230 }