src/soc/intel/meteorlake/pcie_rp.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <intelblocks/pcie_rp.h>
   4 #include <soc/pci_devs.h>
   5 #include <soc/pcie.h>
   6 #include <soc/soc_info.h>
   7
   8 /*
   9  * TBT's LCAP registers are returning port index which starts from 0x10 (Usually for other PCIe
  10  * root ports index starts from 1). Thus keeping lcap_port_base 0x10 for TBT, so that coreboot's
  11  * PCIe remapping logic can return correct index (0-based)
  12  */
  13
  14 static const struct pcie_rp_group tbt_rp_groups[] = {
  15         { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 0x10 },
  16         { 0 }
  17 };
  18
  19 static const struct pcie_rp_group mtlp_rp_groups[] = {
  20         { .slot = PCI_DEV_SLOT_PCIE_1, .start = 0, .count = 8, .lcap_port_base = 1 },
  21         { .slot = PCI_DEV_SLOT_PCIE_2, .start = 0, .count = 3, .lcap_port_base = 1 },
  22         { .slot = PCI_DEV_SLOT_PCIE_3, .start = 0, .count = 1, .lcap_port_base = 1 },
  23         { 0 }
  24 };
  25
  26 const struct pcie_rp_group *get_pcie_rp_table(void)
  27 {
  28         return mtlp_rp_groups;
  29 }
  30
  31 const struct pcie_rp_group *get_tbt_pcie_rp_table(void)
  32 {
  33         return tbt_rp_groups;
  34 }
  35
  36 enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev)
  37 {
  38         return PCIE_RP_PCH;
  39 }
  40
  41 int soc_get_cpu_rp_vw_idx(const struct device *dev)
  42 {
  43         return -1;
  44 }