src/soc/intel/meteorlake/pmc.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3
   4 #include <acpi/acpigen.h>
   5 #include <console/console.h>
   6 #include <device/mmio.h>
   7 #include <device/device.h>
   8 #include <drivers/intel/pmc_mux/chip.h>
   9 #include <intelblocks/acpi.h>
  10 #include <intelblocks/pmc.h>
  11 #include <intelblocks/pmc_ipc.h>
  12 #include <intelblocks/pmclib.h>
  13 #include <intelblocks/rtc.h>
  14 #include <soc/cpu.h>
  15 #include <soc/pci_devs.h>
  16 #include <soc/pm.h>
  17 #include <soc/soc_chip.h>
  18 #include <static.h>
  19 #include <stdint.h>
  20 #include <bootstate.h>
  21
  22 #define PMC_HID         "INTC1026"
  23
  24 static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)
  25 {
  26         uint32_t reg;
  27         uint8_t *pmcbase = pmc_mmio_regs();
  28
  29         printk(BIOS_DEBUG, "%sabling Deep S%c\n",
  30                 enable ? "En" : "Dis", sx + '0');
  31         reg = read32(pmcbase + offset);
  32         if (enable)
  33                 reg |= mask;
  34         else
  35                 reg &= ~mask;
  36         write32(pmcbase + offset, reg);
  37 }
  38
  39 static void config_deep_s5(int on_ac, int on_dc)
  40 {
  41         /* Treat S4 the same as S5. */
  42         config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac);
  43         config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc);
  44         config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac);
  45         config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc);
  46 }
  47
  48 static void config_deep_s3(int on_ac, int on_dc)
  49 {
  50         config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac);
  51         config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc);
  52 }
  53
  54 static void config_deep_sx(uint32_t deepsx_config)
  55 {
  56         uint32_t reg;
  57         uint8_t *pmcbase = pmc_mmio_regs();
  58
  59         reg = read32(pmcbase + DSX_CFG);
  60         reg &= ~DSX_CFG_MASK;
  61         reg |= deepsx_config;
  62         write32(pmcbase + DSX_CFG, reg);
  63 }
  64
  65 static void soc_pmc_enable(struct device *dev)
  66 {
  67         const config_t *config = config_of_soc();
  68
  69         rtc_init();
  70
  71         pmc_set_power_failure_state(true);
  72         pmc_gpe_init();
  73
  74         config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
  75         config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
  76         config_deep_sx(config->deep_sx_config);
  77 }
  78
  79 static void soc_pmc_read_resources(struct device *dev)
  80 {
  81         struct resource *res;
  82
  83         /* Add the fixed MMIO resource */
  84         mmio_range(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE);
  85
  86         /* Add the fixed I/O resource */
  87         res = new_resource(dev, 1);
  88         res->base = (resource_t)ACPI_BASE_ADDRESS;
  89         res->size = (resource_t)ACPI_BASE_SIZE;
  90         res->limit = res->base + res->size - 1;
  91         res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  92 }
  93
  94 static void soc_pmc_fill_ssdt(const struct device *dev)
  95 {
  96         const char *scope = acpi_device_scope(dev);
  97         const char *name = acpi_device_name(dev);
  98         if (!scope || !name)
  99                 return;
 100
 101         acpigen_write_scope(scope);
 102         acpigen_write_device(name);
 103
 104         acpigen_write_name_string("_HID", PMC_HID);
 105         acpigen_write_name_string("_DDN", "Intel(R) Meteor Lake IPC Controller");
 106         /* Hide the device so that Windows does not complain on missing driver */
 107         acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON);
 108
 109         /*
 110          * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF).
 111          * The PMC gets 0xFE000000 - 0xFE00FFFF.
 112          */
 113         acpigen_write_name("_CRS");
 114         acpigen_write_resourcetemplate_header();
 115         acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE);
 116         acpigen_write_resourcetemplate_footer();
 117
 118         /* Define IPC Write Method */
 119         if (CONFIG(PMC_IPC_ACPI_INTERFACE))
 120                 pmc_ipc_acpi_fill_ssdt();
 121
 122         acpigen_pop_len(); /* PMC Device */
 123         acpigen_pop_len(); /* Scope */
 124
 125         if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP)) {
 126                 const struct soc_pmc_lpm mtl_pmc_lpm = {
 127                         .num_substates = 8,
 128                         .num_req_regs = 6,
 129                         .lpm_ipc_offset = 0x1000,
 130                         .req_reg_stride = 0x30,
 131                         .lpm_enable_mask = get_supported_lpm_mask(),
 132                 };
 133
 134                 generate_acpi_power_engine_with_lpm(&mtl_pmc_lpm);
 135         }
 136
 137         printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name,
 138                dev_path(dev));
 139 }
 140
 141 static void soc_pmc_init(struct device *dev)
 142 {
 143         /*
 144          * pmc_set_acpi_mode() should be delayed until BS_DEV_INIT in order
 145          * to ensure the ordering does not break the assumptions that other
 146          * drivers make about ACPI mode (e.g. Chrome EC). Since it disables
 147          * ACPI mode, other drivers may take different actions based on this
 148          * (e.g. Chrome EC will flush any pending hostevent bits). Because
 149          * TGL has its PMC device available for device_operations, it can be
 150          * done from the "ops->init" callback.
 151          */
 152         pmc_set_acpi_mode();
 153
 154         /*
 155          * Disable ACPI PM timer based on Kconfig
 156          *
 157          * Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
 158          * Disabling ACPI PM timer also switches off TCO
 159          */
 160         if (!CONFIG(USE_PM_ACPI_TIMER))
 161                 setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
 162 }
 163
 164 static void pm1_enable_pwrbtn_smi(void *unused)
 165 {
 166         /* Enable power button SMI after BS_DEV_INIT_CHIPS (FSP-S) is done. */
 167         pmc_update_pm1_enable(PWRBTN_EN);
 168 }
 169
 170 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
 171
 172 /*
 173  * `pmc_final` function is native implementation of equivalent events performed by
 174  * each FSP NotifyPhase() API invocations.
 175  *
 176  *
 177  * Clear PMCON status bits (Global Reset/Power Failure/Host Reset Status bits)
 178  *
 179  * Perform the PMCON status bit clear operation from `.final`
 180  * to cover any such chances where later boot stage requested a global
 181  * reset and PMCON status bit remains set.
 182  */
 183 static void pmc_final(struct device *dev)
 184 {
 185         pmc_clear_pmcon_sts();
 186 }
 187
 188 struct device_operations pmc_ops = {
 189         .read_resources   = soc_pmc_read_resources,
 190         .set_resources    = noop_set_resources,
 191         .init             = soc_pmc_init,
 192         .enable           = soc_pmc_enable,
 193 #if CONFIG(HAVE_ACPI_TABLES)
 194         .acpi_fill_ssdt   = soc_pmc_fill_ssdt,
 195 #endif
 196         .scan_bus         = scan_static_bus,
 197         .final            = pmc_final,
 198 };