mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters
[coreboot2.git] / src / soc / intel / meteorlake / xhci.c
blob9b4ac1b066f23939c5d5674ecc611c9f9d064108
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/pci_type.h>
4 #include <intelblocks/xhci.h>
5 #include <soc/pci_devs.h>
7 #define XHCI_USB2_PORT_STATUS_REG 0x480
8 #define XHCI_USB3_PORT_STATUS_REG 0x540
9 #define XHCI_USB2_PORT_NUM 10
10 #define XHCI_USB3_PORT_NUM 4
12 #define TCSS_XHCI_USB2_PORT_STATUS_REG 0x480
13 #define TCSS_XHCI_USB3_PORT_STATUS_REG 0x490
14 #define TCSS_XHCI_USB2_PORT_NUM 0
15 #define TCSS_XHCI_USB3_PORT_NUM 4
17 static const struct xhci_usb_info usb_info = {
18 .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG,
19 .num_usb2_ports = XHCI_USB2_PORT_NUM,
20 .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG,
21 .num_usb3_ports = XHCI_USB3_PORT_NUM,
24 static const struct xhci_usb_info tcss_usb_info = {
25 .usb2_port_status_reg = TCSS_XHCI_USB2_PORT_STATUS_REG,
26 .num_usb2_ports = TCSS_XHCI_USB2_PORT_NUM,
27 .usb3_port_status_reg = TCSS_XHCI_USB3_PORT_STATUS_REG,
28 .num_usb3_ports = TCSS_XHCI_USB3_PORT_NUM,
31 const struct xhci_usb_info *soc_get_xhci_usb_info(pci_devfn_t xhci_dev)
33 if (xhci_dev == PCI_DEVFN_XHCI)
34 return &usb_info;
35 else if (xhci_dev == PCI_DEVFN_TCSS_XHCI)
36 return &tcss_usb_info;
38 return NULL;