src/soc/intel/pantherlake/meminit.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <fsp/util.h>
   4 #include <soc/meminit.h>
   5
   6 #define LP5_PHYSICAL_CH_WIDTH           16
   7 #define LP5_CHANNELS                    CHANNEL_COUNT(LP5_PHYSICAL_CH_WIDTH)
   8
   9 #define DDR5_PHYSICAL_CH_WIDTH          32
  10 #define DDR5_CHANNELS                   CHANNEL_COUNT(DDR5_PHYSICAL_CH_WIDTH)
  11
  12 static void set_rcomp_config(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg)
  13 {
  14         if (mb_cfg->rcomp.resistor)
  15                 mem_cfg->RcompResistor = mb_cfg->rcomp.resistor;
  16
  17         for (size_t i = 0; i < ARRAY_SIZE(mem_cfg->RcompTarget); i++)
  18                 if (mb_cfg->rcomp.targets[i])
  19                         mem_cfg->RcompTarget[i] = mb_cfg->rcomp.targets[i];
  20 }
  21
  22 static void meminit_lp5x(FSP_M_CONFIG *mem_cfg, const struct mem_lp5x_config *lp5x_config)
  23 {
  24         mem_cfg->DqPinsInterleaved = 0;
  25         mem_cfg->Lp5CccConfig = lp5x_config->ccc_config;
  26 }
  27
  28 static void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct mem_ddr_config *ddr_config)
  29 {
  30         mem_cfg->DqPinsInterleaved = ddr_config->dq_pins_interleaved;
  31 }
  32
  33 static const struct soc_mem_cfg soc_mem_cfg[] = {
  34         [MEM_TYPE_DDR5] = {
  35                 .num_phys_channels = DDR5_CHANNELS,
  36                 .phys_to_mrc_map = {
  37                         [0] = 0,
  38                         [1] = 1,
  39                         [2] = 4,
  40                         [3] = 5,
  41                 },
  42                 .md_phy_masks = {
  43                         /*
  44                          * Physical channels 0 and 1 are populated in case of
  45                          * half-populated configurations.
  46                          */
  47                         .half_channel = BIT(0) | BIT(1),
  48                         /* In mixed topology, channels 2 and 3 are always memory-down. */
  49                         .mixed_topo = BIT(2) | BIT(3),
  50                 },
  51         },
  52         [MEM_TYPE_LP5X] = {
  53                 .num_phys_channels = LP5_CHANNELS,
  54                 .phys_to_mrc_map = {
  55                         [0] = 0,
  56                         [1] = 1,
  57                         [2] = 2,
  58                         [3] = 3,
  59                         [4] = 4,
  60                         [5] = 5,
  61                         [6] = 6,
  62                         [7] = 7,
  63                 },
  64                 .md_phy_masks = {
  65                         /*
  66                          * Physical channels 0, 1, 2 and 3 are populated in case
  67                          * of half-populated configurations.
  68                          */
  69                         .half_channel = BIT(0) | BIT(1) | BIT(2) | BIT(3),
  70                         /* LP5x does not support mixed topology. */
  71                 },
  72         },
  73 };
  74
  75 static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data)
  76 {
  77         uint64_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = {
  78                 [0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, },
  79                 [1] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr011, },
  80                 [2] = { &mem_cfg->MemorySpdPtr020, &mem_cfg->MemorySpdPtr021, },
  81                 [3] = { &mem_cfg->MemorySpdPtr030, &mem_cfg->MemorySpdPtr031, },
  82                 [4] = { &mem_cfg->MemorySpdPtr100, &mem_cfg->MemorySpdPtr101, },
  83                 [5] = { &mem_cfg->MemorySpdPtr110, &mem_cfg->MemorySpdPtr111, },
  84                 [6] = { &mem_cfg->MemorySpdPtr120, &mem_cfg->MemorySpdPtr121, },
  85                 [7] = { &mem_cfg->MemorySpdPtr130, &mem_cfg->MemorySpdPtr131, },
  86         };
  87         uint8_t *disable_channel_upds[MRC_CHANNELS] = {
  88                 &mem_cfg->DisableMc0Ch0,
  89                 &mem_cfg->DisableMc0Ch1,
  90                 &mem_cfg->DisableMc0Ch2,
  91                 &mem_cfg->DisableMc0Ch3,
  92                 &mem_cfg->DisableMc1Ch0,
  93                 &mem_cfg->DisableMc1Ch1,
  94                 &mem_cfg->DisableMc1Ch2,
  95                 &mem_cfg->DisableMc1Ch3,
  96         };
  97         size_t ch, dimm;
  98
  99         mem_cfg->MemorySpdDataLen = data->spd_len;
 100
 101         for (ch = 0; ch < MRC_CHANNELS; ch++) {
 102                 uint8_t *disable_channel_ptr = disable_channel_upds[ch];
 103                 bool enable_channel = 0;
 104
 105                 for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
 106                         uint64_t *spd_ptr = spd_upds[ch][dimm];
 107
 108                         *spd_ptr = data->spd[ch][dimm];
 109                         if (*spd_ptr)
 110                                 enable_channel = 1;
 111                 }
 112                 *disable_channel_ptr = !enable_channel;
 113         }
 114 }
 115
 116 static void mem_init_dq_dqs_upds(void *upds[MRC_CHANNELS], const void *map, size_t upd_size,
 117                                  const struct mem_channel_data *data, bool auto_detect)
 118 {
 119         for (size_t i = 0; i < MRC_CHANNELS; i++, map += upd_size) {
 120                 if (auto_detect || !channel_is_populated(i, MRC_CHANNELS,
 121                                                          data->ch_population_flags))
 122                         memset(upds[i], 0, upd_size);
 123                 else
 124                         memcpy(upds[i], map, upd_size);
 125         }
 126 }
 127
 128 static void mem_init_dq_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data,
 129                              const struct mb_cfg *mb_cfg, bool auto_detect)
 130 {
 131         const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramMc0Ch0);
 132         void *dq_upds[MRC_CHANNELS] = {
 133                 &mem_cfg->DqMapCpu2DramMc0Ch0,
 134                 &mem_cfg->DqMapCpu2DramMc0Ch1,
 135                 &mem_cfg->DqMapCpu2DramMc0Ch2,
 136                 &mem_cfg->DqMapCpu2DramMc0Ch3,
 137                 &mem_cfg->DqMapCpu2DramMc1Ch0,
 138                 &mem_cfg->DqMapCpu2DramMc1Ch1,
 139                 &mem_cfg->DqMapCpu2DramMc1Ch2,
 140                 &mem_cfg->DqMapCpu2DramMc1Ch3,
 141         };
 142
 143         _Static_assert(sizeof(mem_cfg->DqMapCpu2DramMc0Ch0) == CONFIG_MRC_CHANNEL_WIDTH,
 144                        "Incorrect DQ UPD size!");
 145
 146         mem_init_dq_dqs_upds(dq_upds, mb_cfg->dq_map, upd_size, data, auto_detect);
 147 }
 148
 149 static void mem_init_dqs_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data,
 150                               const struct mb_cfg *mb_cfg, bool auto_detect)
 151 {
 152         const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramMc0Ch0);
 153         void *dqs_upds[MRC_CHANNELS] = {
 154                 &mem_cfg->DqsMapCpu2DramMc0Ch0,
 155                 &mem_cfg->DqsMapCpu2DramMc0Ch1,
 156                 &mem_cfg->DqsMapCpu2DramMc0Ch2,
 157                 &mem_cfg->DqsMapCpu2DramMc0Ch3,
 158                 &mem_cfg->DqsMapCpu2DramMc1Ch0,
 159                 &mem_cfg->DqsMapCpu2DramMc1Ch1,
 160                 &mem_cfg->DqsMapCpu2DramMc1Ch2,
 161                 &mem_cfg->DqsMapCpu2DramMc1Ch3,
 162         };
 163
 164         _Static_assert(sizeof(mem_cfg->DqsMapCpu2DramMc0Ch0) == CONFIG_MRC_CHANNEL_WIDTH / 8,
 165                        "Incorrect DQS UPD size!");
 166
 167         mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data, auto_detect);
 168 }
 169
 170 #define DDR5_CH_DIMM_OFFSET(ch, dimm)        ((ch) * CONFIG_DIMMS_PER_CHANNEL + (dimm))
 171
 172 static void ddr5_fill_dimm_module_info(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg,
 173                                        const struct mem_spd *spd_info)
 174 {
 175         for (size_t ch = 0; ch < soc_mem_cfg[MEM_TYPE_DDR5].num_phys_channels; ch++) {
 176                 for (size_t dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
 177                         size_t mrc_ch = soc_mem_cfg[MEM_TYPE_DDR5].phys_to_mrc_map[ch];
 178                         mem_cfg->SpdAddressTable[DDR5_CH_DIMM_OFFSET(mrc_ch, dimm)] =
 179                                 spd_info->smbus[ch].addr_dimm[dimm] << 1;
 180                 }
 181         }
 182         mem_init_dq_upds(mem_cfg, NULL, mb_cfg, true);
 183         mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true);
 184 }
 185
 186 void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
 187                  const struct mem_spd *spd_info, bool half_populated)
 188 {
 189         struct mem_channel_data data;
 190         bool dq_dqs_auto_detect = false;
 191         FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;
 192
 193         mem_cfg->ECT = mb_cfg->ect;
 194         mem_cfg->UserBd = mb_cfg->user_bd;
 195         set_rcomp_config(mem_cfg, mb_cfg);
 196
 197         switch (mb_cfg->type) {
 198         case MEM_TYPE_DDR5:
 199                 meminit_ddr(mem_cfg, &mb_cfg->ddr_config);
 200                 dq_dqs_auto_detect = true;
 201                 /*
 202                  * TODO: Drop this workaround once SMBus driver in coreboot is
 203                  * updated to support DDR5 EEPROM reading.
 204                  */
 205                 if (spd_info->topo == MEM_TOPO_DIMM_MODULE) {
 206                         ddr5_fill_dimm_module_info(mem_cfg, mb_cfg, spd_info);
 207                         return;
 208                 }
 209                 break;
 210         case MEM_TYPE_LP5X:
 211                 meminit_lp5x(mem_cfg, &mb_cfg->lp5x_config);
 212                 break;
 213         default:
 214                 die("Unsupported memory type(%d)\n", mb_cfg->type);
 215         }
 216
 217         mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info,
 218                                   half_populated, &data);
 219         mem_init_spd_upds(mem_cfg, &data);
 220         mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect);
 221         mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect);
 222 }