src/soc/intel/tigerlake/acpi/southbridge.asl

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <intelblocks/itss.h>
   4 #include <intelblocks/pcr.h>
   5 #include <soc/pcr_ids.h>
   6
   7 /* PCR access */
   8 #include <soc/intel/common/acpi/pch_pcr.asl>
   9
  10 /* PCH clock */
  11 #include "camera_clock_ctl.asl"
  12
  13 /* GPIO controller */
  14 #if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
  15 #include "gpio_pch_h.asl"
  16 #else
  17 #include "gpio.asl"
  18 #endif
  19
  20 /* ESPI 0:1f.0 */
  21 #include <soc/intel/common/block/acpi/acpi/lpc.asl>
  22
  23 /* PCH HDA */
  24 #include "pch_hda.asl"
  25
  26 /* PCIE Ports */
  27 #include "pcie.asl"
  28
  29 /* Serial IO */
  30 #include "serialio.asl"
  31
  32 /* SMBus 0:1f.4 */
  33 #include <soc/intel/common/block/acpi/acpi/smbus.asl>
  34
  35 /* ISH 0:12.0 */
  36 #include <soc/intel/common/block/acpi/acpi/ish.asl>
  37
  38 /* USB XHCI 0:14.0 */
  39 #include "xhci.asl"
  40
  41 /* PCI _OSC */
  42 #include <soc/intel/common/acpi/pci_osc.asl>
  43
  44 /* GbE 0:1f.6 */
  45 #include <soc/intel/common/block/acpi/acpi/pch_glan.asl>