src/soc/intel/tigerlake/systemagent.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * This file is created based on Intel Tiger Lake Processor SA Datasheet
   5  * Document number: 571131
   6  * Chapter number: 3
   7  */
   8
   9 #include <console/console.h>
  10 #include <device/device.h>
  11 #include <delay.h>
  12 #include <device/pci.h>
  13 #include <device/pci_ids.h>
  14 #include <device/pci_ops.h>
  15 #include <intelblocks/power_limit.h>
  16 #include <intelblocks/systemagent.h>
  17 #include <soc/iomap.h>
  18 #include <soc/soc_chip.h>
  19 #include <soc/systemagent.h>
  20 #include <static.h>
  21
  22 /*
  23  * SoC implementation
  24  *
  25  * Add all known fixed memory ranges for Host Controller/Memory
  26  * controller.
  27  */
  28 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
  29 {
  30         static const struct sa_mmio_descriptor soc_fixed_resources[] = {
  31                 { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
  32                                 "PCIEXBAR" },
  33                 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
  34                 { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
  35                 { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
  36                 { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
  37                 { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
  38         };
  39
  40         sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
  41                         ARRAY_SIZE(soc_fixed_resources));
  42
  43         /* Add Vt-d resources if VT-d is enabled */
  44         if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
  45                 return;
  46
  47         sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
  48                         ARRAY_SIZE(soc_vtd_resources));
  49 }
  50
  51 /*
  52  * SoC implementation
  53  *
  54  * Perform System Agent Initialization during Ramstage phase.
  55  */
  56 void soc_systemagent_init(struct device *dev)
  57 {
  58         struct soc_power_limits_config *soc_config;
  59         struct device *sa;
  60         uint16_t sa_pci_id;
  61         config_t *config;
  62
  63         /* Get System Agent PCI ID */
  64         sa = pcidev_path_on_root(SA_DEVFN_ROOT);
  65         sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF;
  66
  67         /* Enable Power Aware Interrupt Routing */
  68         enable_power_aware_intr();
  69
  70         /* Enable BIOS Reset CPL */
  71         enable_bios_reset_cpl();
  72
  73         /* Configure turbo power limits 1ms after reset complete bit */
  74         mdelay(1);
  75         config = config_of_soc();
  76
  77         /*
  78          * Choose a power limits configuration based on the SoC SKU,
  79          * differentiated here based on SA PCI ID.
  80          */
  81         switch (sa_pci_id) {
  82         case PCI_DID_INTEL_TGL_ID_U_2_2:
  83                 soc_config = &config->power_limits_config[POWER_LIMITS_U_2_CORE];
  84                 break;
  85         case PCI_DID_INTEL_TGL_ID_U_4_2:
  86                 soc_config = &config->power_limits_config[POWER_LIMITS_U_4_CORE];
  87                 break;
  88         case PCI_DID_INTEL_TGL_ID_Y_2_2:
  89                 soc_config = &config->power_limits_config[POWER_LIMITS_Y_2_CORE];
  90                 break;
  91         case PCI_DID_INTEL_TGL_ID_Y_4_2:
  92                 soc_config = &config->power_limits_config[POWER_LIMITS_Y_4_CORE];
  93                 break;
  94         case PCI_DID_INTEL_TGL_ID_H_6_1:
  95                 soc_config = &config->power_limits_config[POWER_LIMITS_H_6_CORE];
  96                 break;
  97         case PCI_DID_INTEL_TGL_ID_H_8_1:
  98                 soc_config = &config->power_limits_config[POWER_LIMITS_H_8_CORE];
  99                 break;
 100         default:
 101                 printk(BIOS_ERR, "TGL: unknown SA ID: 0x%4x, skipping power limits "
 102                        "configuration\n", sa_pci_id);
 103                 return;
 104         }
 105
 106         set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
 107 }
 108
 109 uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
 110 {
 111         switch (capid0_a_ddrsz) {
 112         case 1:
 113                 return 8192;
 114         case 2:
 115                 return 4096;
 116         case 3:
 117                 return 2048;
 118         default:
 119                 return 65536;
 120         }
 121 }