src/soc/intel/xeon_sp/ibl/soc_pch.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/pci_ops.h>
   5 #include <intelblocks/pcr.h>
   6 #include <soc/bootblock.h>
   7 #include <soc/pci_devs.h>
   8 #include <soc/pcr_ids.h>
   9 #include <soc/soc_pch.h>
  10
  11 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE   0x600
  12 #define PCR_PSFX_TO_SHDW_BAR4           0x10
  13 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN     0x01
  14 #define PCR_PSFX_T0_SHDW_PCIEN          0x1C
  15
  16 static void soc_config_acpibase(void)
  17 {
  18         uint32_t pmc_reg_value;
  19         uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE;
  20
  21         pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
  22
  23         if (pmc_reg_value != 0xffffffff) {
  24                 /* Disable Io Space before changing the address */
  25                 pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
  26                                 ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);
  27                 /* Program ABASE in PSF3 PMC space BAR4*/
  28                 pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4,
  29                                 ACPI_BASE_ADDRESS);
  30                 /* Enable IO Space */
  31                 pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
  32                                 ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);
  33         }
  34         /* Enable Bus Master and IO Space */
  35         pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_IO | PCI_COMMAND_MASTER));
  36
  37         uint16_t data = pcr_read16(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
  38         printk(BIOS_INFO, "%s : pmbase = %x\n", __func__, (int)data);
  39 }
  40
  41 void bootblock_pch_init(void)
  42 {
  43         /*
  44          * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT
  45          */
  46         soc_config_acpibase();
  47 }
  48
  49 void early_pch_init(void)
  50 {
  51 }