commonlib: Add new "ESE completed AUnit loading" TS
[coreboot2.git] / src / soc / intel / xeon_sp / ibl / soc_pmutil.c
blob406114e6acf0312d070dc95e4e45492276860dad
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 /*
4 * Helper functions for dealing with power management registers
5 * and the differences between PCH variants.
6 */
8 #define __SIMPLE_DEVICE__
10 #include <console/console.h>
11 #include <device/pci.h>
12 #include <intelblocks/pmclib.h>
13 #include <intelblocks/rtc.h>
14 #include <soc/pm.h>
15 #include <soc/pmc.h>
17 uint8_t *pmc_mmio_regs(void)
19 /* PMC PWRMBASE can be hidden after FSP-S so can't be accessed using PCI CSR,
20 * hence use hard-coded address */
21 return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
24 uintptr_t soc_read_pmc_base(void)
26 return (uintptr_t)(pmc_mmio_regs());
29 uint32_t *soc_pmc_etr_addr(void)
32 * The pointer returned must not be cached, because the address depends on the
33 * MMCONF base address and the assigned PCI bus number, which both may change
34 * during the boot process!
36 return (uint32_t *)(soc_read_pmc_base() + ETR);
39 int soc_get_rtc_failed(void)
41 uint32_t pmcon_b = read32(pmc_mmio_regs() + GEN_PMCON_B);
42 int rtc_fail = !!(pmcon_b & RTC_BATTERY_DEAD);
44 if (rtc_fail)
45 printk(BIOS_ERR, "%s: RTC battery dead or removed\n", __func__);
47 return rtc_fail;
51 * Set which power state system will be after reapplying
52 * the power (from G3 State)
54 void pmc_soc_set_afterg3_en(const bool on)
56 uint8_t reg8;
57 uint8_t *const pmcbase = pmc_mmio_regs();
59 reg8 = read8(pmcbase + GEN_PMCON_A);
60 if (on)
61 reg8 &= ~SLEEP_AFTER_POWER_FAIL;
62 else
63 reg8 |= SLEEP_AFTER_POWER_FAIL;
64 write8(pmcbase + GEN_PMCON_A, reg8);
67 void pmc_lockdown_config(void)
69 /* Make sure payload/OS can't trigger global reset */
70 pmc_global_reset_disable_and_lock();
72 /* Lock PMC stretch policy */
73 pmc_or_mmio32(GEN_PMCON_B, SLP_STR_POL_LOCK);
74 pmc_or_mmio32(PM_CFG, PMC_LOCK);