src/soc/intel/xeon_sp/spr/chip.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 #include <acpi/acpigen_pci.h>
   3 #include <arch/ioapic.h>
   4 #include <console/console.h>
   5 #include <console/debug.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <device/pci.h>
   8 #include <device/pci_ids.h>
   9 #include <device/pciexp.h>
  10 #include <intelblocks/acpi.h>
  11 #include <intelblocks/gpio.h>
  12 #include <intelblocks/lpc_lib.h>
  13 #include <intelblocks/p2sb.h>
  14 #include <intelblocks/pcr.h>
  15 #include <intelblocks/tco.h>
  16 #include <soc/acpi.h>
  17 #include <soc/chip_common.h>
  18 #include <soc/crashlog.h>
  19 #include <soc/numa.h>
  20 #include <soc/p2sb.h>
  21 #include <soc/pch.h>
  22 #include <soc/soc_pch.h>
  23 #include <soc/pci_devs.h>
  24 #include <soc/ramstage.h>
  25 #include <soc/soc_util.h>
  26 #include <soc/util.h>
  27 #include <soc/xhci.h>
  28
  29 __weak void mainboard_silicon_init_params(FSPS_UPD *params)
  30 {
  31 }
  32
  33 /* UPD parameters to be initialized before SiliconInit */
  34 void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
  35 {
  36         mainboard_silicon_init_params(silupd);
  37 }
  38
  39 static struct device_operations cpu_bus_ops = {
  40         .read_resources = noop_read_resources,
  41         .set_resources = noop_set_resources,
  42         .init = mp_cpu_bus_init,
  43         .acpi_fill_ssdt = generate_cpu_entries,
  44 };
  45
  46 struct pci_operations soc_pci_ops = {
  47         .set_subsystem = pci_dev_set_subsystem,
  48 };
  49
  50 static void chip_enable_dev(struct device *dev)
  51 {
  52         /* Set the operations if it is a special bus type */
  53         if (dev->path.type == DEVICE_PATH_DOMAIN) {
  54                 /* domain ops are assigned at their creation */
  55         } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
  56                 dev->ops = &cpu_bus_ops;
  57         } else if (dev->path.type == DEVICE_PATH_GPIO) {
  58                 block_gpio_enable(dev);
  59         }
  60 }
  61
  62 static void set_pcu_locks(void)
  63 {
  64         struct device *dev = NULL;
  65
  66         while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR0_DEVID, dev))) {
  67                 printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev));
  68                 pci_or_config32(dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK);
  69                 pci_or_config32(dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR,
  70                                 PKG_PWR_LIM_LOCK_UPR);
  71                 pci_or_config32(dev, PCU_CR0_TURBO_ACTIVATION_RATIO,
  72                                 TURBO_ACTIVATION_RATIO_LOCK);
  73         }
  74
  75         dev = NULL;
  76         while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR2_DEVID, dev))) {
  77                 printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev));
  78                 pci_or_config32(dev, PCU_CR2_DRAM_POWER_INFO_UPR,
  79                                 DRAM_POWER_INFO_LOCK_UPR);
  80                 pci_or_config32(dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT_UPR,
  81                                 PP_PWR_LIM_LOCK_UPR);
  82         }
  83
  84         dev = NULL;
  85         while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR3_DEVID, dev))) {
  86                 printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev));
  87                 pci_or_config32(dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK);
  88         }
  89
  90         dev = NULL;
  91         while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR6_DEVID, dev))) {
  92                 printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev));
  93                 pci_or_config32(dev, PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR,
  94                                 PLT_PWR_LIM_LOCK_UPR);
  95                 pci_or_config32(dev, PCU_CR6_PLATFORM_POWER_INFO_CFG_UPR,
  96                                 PLT_PWR_INFO_LOCK_UPR);
  97         }
  98 }
  99
 100 static void chip_final(void *data)
 101 {
 102         /* Lock SBI */
 103         pci_or_config32(PCH_DEV_P2SB, P2SBC, SBILOCK);
 104
 105         /* LOCK PAM */
 106         pci_or_config32(pcidev_path_on_root(PCI_DEVFN(0, 0)), 0x80, 1 << 0);
 107
 108         set_pcu_locks();
 109         tco_lockdown();
 110
 111         p2sb_hide();
 112
 113         /* Accessing xHCI CSR needs to be done after PCI enumeration. */
 114         lock_oc_cfg(false);
 115         mainboard_override_usb_oc();
 116         lock_oc_cfg(true);
 117         /* Disable CPU Crashlog to avoid conflict between CPU Crashlog and BMC ACD. */
 118         disable_cpu_crashlog();
 119
 120         set_bios_init_completion();
 121 }
 122
 123 static void chip_init(void *data)
 124 {
 125         printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
 126         fsp_silicon_init();
 127
 128         setup_pds();
 129         attach_iio_stacks();
 130
 131         override_hpet_ioapic_bdf();
 132         pch_enable_ioapic();
 133         pch_lock_dmictl();
 134         p2sb_unhide();
 135         lock_gpio(false);
 136         mainboard_override_fsp_gpio();
 137         lock_gpio(true);
 138 }
 139
 140 struct chip_operations soc_intel_xeon_sp_spr_ops = {
 141         .name = "Intel SapphireRapids-SP",
 142         .enable_dev = chip_enable_dev,
 143         .init = chip_init,
 144         .final = chip_final,
 145 };
 146
 147 void lock_gpio(bool lock)
 148 {
 149         if (lock) {
 150                 pcr_write32(gpio_get_pad_portid(GPPC_B0), PAD_CFG_LOCK_B, 0xffffffff);
 151                 pcr_write32(gpio_get_pad_portid(GPP_D0), PAD_CFG_LOCK_D, 0xffffffff);
 152         } else {
 153                 pcr_write32(gpio_get_pad_portid(GPPC_B0), PAD_CFG_LOCK_B, 0);
 154                 pcr_write32(gpio_get_pad_portid(GPP_D0), PAD_CFG_LOCK_D, 0);
 155         }
 156 }
 157
 158 /* Root Complex Event Collector */
 159 static void rcec_init(struct device *dev)
 160 {
 161         /* Set up RCEC EA extended capability, section 7.9.10 of PCIe 5.0 spec */
 162         const unsigned int rcecea_cap =
 163                 pciexp_find_extended_cap(dev, PCIE_EXT_CAP_RCECEA_ID, 0);
 164         if (!rcecea_cap)
 165                 return;
 166
 167         pci_devfn_t ecrc_bdf = PCI_BDF(dev);
 168         uint32_t ecrc_bus = (ecrc_bdf >> 20) & 0xFFF;
 169         uint32_t ecrc_dev = (ecrc_bdf >> 15) & 0x1F;
 170
 171         /*
 172          * Find all CXL devices, and match them with RCEC.
 173          * With CXL 1.1, the bus# of CXL device (RCiEP) is 1 bigger than
 174          * the bus# of RCEC.
 175          */
 176         uint32_t ep_bus;
 177         uint8_t i;
 178         for (i = 0; i < pds.num_pds; i++) {
 179                 if (pds.pds[i].pd_type != PD_TYPE_GENERIC_INITIATOR)
 180                         continue;
 181                 ep_bus = PCI_BDF(pds.pds[i].dev) >> 20;
 182                 if (ep_bus == ecrc_bus + 1)
 183                         break;
 184         }
 185         if (i == pds.num_pds)
 186                 return;
 187
 188         printk(BIOS_DEBUG, "ep_bus: %x, ecrc_dev: %x\n", ep_bus, ecrc_dev);
 189         u32 rcecea_bitmap = 0x1 << ecrc_dev;
 190         u32 rcecea_busnum = (ep_bus << 8) | (ep_bus << 16);
 191         pci_write_config32(dev, rcecea_cap + PCI_RCECEA_BITMAP, rcecea_bitmap);
 192         pci_write_config32(dev, rcecea_cap + PCI_RCECEA_BUSNUM, rcecea_busnum);
 193 }
 194
 195 #define SPR_IEH 0x0b23
 196
 197 static const unsigned short rcec_ids[] = {
 198         SPR_IEH,
 199         0
 200 };
 201
 202 static struct device_operations rcec_ops = {
 203         .read_resources = pci_dev_read_resources,
 204         .set_resources = pci_dev_set_resources,
 205         .enable_resources = pci_dev_enable_resources,
 206         .init = rcec_init,
 207         .ops_pci = &soc_pci_ops,
 208 };
 209
 210 static const struct pci_driver rcec_driver __pci_driver = {
 211         .ops = &rcec_ops,
 212         .vendor = PCI_VID_INTEL,
 213         .devices = rcec_ids,
 214 };