soc/intel/xeon_sp: Allow OS to control LTR and AER
[coreboot2.git] / src / soc / mediatek / common / mt6373.c
blob1d5e1e25beda8c1fbff5f8ab43d69031643378fd
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <assert.h>
4 #include <console/console.h>
5 #include <delay.h>
6 #include <soc/mt6373.h>
7 #include <soc/pmif.h>
8 #include <timer.h>
10 static const struct mt6373_setting key_protect_setting[] = {
11 {0x39E, 0x8C, 0xFF, 0},
12 {0x39F, 0x9C, 0xFF, 0},
13 {0xFAB, 0x73, 0xFF, 0},
14 {0xFAC, 0x63, 0xFF, 0},
15 {0x142A, 0x43, 0xFF, 0},
16 {0x142B, 0x55, 0xFF, 0},
17 {0x3A7, 0x8C, 0xFF, 0},
18 {0x3A8, 0x9C, 0xFF, 0},
19 {0xA1A, 0x29, 0xFF, 0},
20 {0xA1B, 0x47, 0xFF, 0},
23 static struct pmif *pmif_arb;
24 static void mt6373_write8(u32 reg, u8 data)
26 assert(pmif_arb);
27 pmif_arb->write(pmif_arb, SPMI_SLAVE_5, reg, data);
30 static u32 mt6373_read_field(u32 reg, u32 mask, u32 shift)
32 assert(pmif_arb);
33 return pmif_arb->read_field(pmif_arb, SPMI_SLAVE_5, reg, mask, shift);
36 void mt6373_write_field(u32 reg, u32 val, u32 mask, u32 shift)
38 assert(pmif_arb);
39 pmif_arb->write_field(pmif_arb, SPMI_SLAVE_5, reg, val, mask, shift);
42 static void pmic_protect_key_setting(bool lock)
44 for (int i = 0; i < ARRAY_SIZE(key_protect_setting); i++)
45 mt6373_write8(key_protect_setting[i].addr,
46 lock ? 0 : key_protect_setting[i].val);
47 printk(BIOS_INFO, "%s done\n", __func__);
50 void mt6373_set_vmc_voltage(u32 vmc_uv)
52 u32 reg_vol, reg_cali;
54 assert(pmif_arb);
56 if (vmc_uv >= 1200000 && vmc_uv <= 1300000)
57 reg_vol = (vmc_uv - 1200000) / 100000;
58 else if (vmc_uv >= 1500000 && vmc_uv <= 1700000)
59 reg_vol = (vmc_uv - 1500000) / 200000 + 2;
60 else if (vmc_uv >= 1800000 && vmc_uv <= 2000000)
61 reg_vol = (vmc_uv - 1800000) / 200000 + 4;
62 else if (vmc_uv >= 2100000 && vmc_uv <= 2200000)
63 reg_vol = (vmc_uv - 2100000) / 100000 + 6;
64 else if (vmc_uv >= 2700000 && vmc_uv <= 3100000)
65 reg_vol = (vmc_uv - 2700000) / 100000 + 8;
66 else if (vmc_uv >= 3300000 && vmc_uv <= 3500000)
67 reg_vol = (vmc_uv - 3300000) / 100000 + 13;
68 else
69 die("ERROR: Unknown vmc voltage %u", vmc_uv);
71 reg_cali = ((vmc_uv / 1000) % 100) / 10;
73 mt6373_write8(MT6373_VMC_ANA_CON1, reg_vol);
74 mt6373_write8(MT6373_VMC_ANA_CON0, reg_cali);
76 printk(BIOS_INFO, "%s: 0x%x, %d\n", __func__, reg_vol, vmc_uv);
79 u32 mt6373_get_vmc_voltage(void)
81 u32 reg_vol, reg_cali, vol;
83 assert(pmif_arb);
85 reg_vol = mt6373_read_field(MT6373_VMC_ANA_CON1, 0xF, 0);
86 reg_cali = mt6373_read_field(MT6373_VMC_ANA_CON0, 0xF, 0);
88 if (reg_vol == 0 || reg_vol == 1)
89 vol = (reg_vol - 0) * 100000 + 1200000;
90 else if (reg_vol == 2 || reg_vol == 3)
91 vol = (reg_vol - 2) * 200000 + 1500000;
92 else if (reg_vol == 4 || reg_vol == 5)
93 vol = (reg_vol - 4) * 200000 + 1800000;
94 else if (reg_vol == 6 || reg_vol == 7)
95 vol = (reg_vol - 6) * 100000 + 2100000;
96 else if (reg_vol >= 8 && reg_vol <= 12)
97 vol = (reg_vol - 8) * 100000 + 2700000;
98 else if (reg_vol >= 13 && reg_vol <= 15)
99 vol = (reg_vol - 13) * 100000 + 3300000;
100 else
101 die("ERROR: Unknown vsim1 reg_vol %x", reg_vol);
103 printk(BIOS_INFO, "%s: reg_vol 0x%x, reg_cali 0x%x, vol %d, %d\n",
104 __func__, reg_vol, reg_cali, vol, (vol + reg_cali * 1000));
106 return (vol + reg_cali * 1000);
109 void mt6373_set_vmch_voltage(u32 vmch_uv)
111 u32 reg_vol, reg_cali;
113 assert(pmif_arb);
115 if (vmch_uv >= 1200000 && vmch_uv <= 1300000)
116 reg_vol = (vmch_uv - 1200000) / 100000;
117 else if (vmch_uv >= 1500000 && vmch_uv <= 1700000)
118 reg_vol = (vmch_uv - 1500000) / 200000 + 2;
119 else if (vmch_uv >= 1800000 && vmch_uv <= 2000000)
120 reg_vol = (vmch_uv - 1800000) / 200000 + 4;
121 else if (vmch_uv >= 2500000 && vmch_uv <= 3100000)
122 reg_vol = (vmch_uv - 2500000) / 100000 + 6;
123 else if (vmch_uv >= 3300000 && vmch_uv <= 3500000)
124 reg_vol = (vmch_uv - 3300000) / 100000 + 13;
125 else
126 die("ERROR: Unknown vmc voltage %u", vmch_uv);
128 reg_cali = ((vmch_uv / 1000) % 100) / 10;
130 mt6373_write8(MT6373_VMCH_ANA_CON1, reg_vol);
131 mt6373_write8(MT6373_VMCH_ANA_CON0, reg_cali);
133 printk(BIOS_INFO, "%s: 0x%x, %d\n", __func__, reg_vol, vmch_uv);
136 u32 mt6373_get_vmch_voltage(void)
138 u32 reg_vol, reg_cali, vol;
140 assert(pmif_arb);
142 reg_vol = mt6373_read_field(MT6373_VMCH_ANA_CON1, 0xF, 0);
143 reg_cali = mt6373_read_field(MT6373_VMCH_ANA_CON0, 0xF, 0);
145 if (reg_vol == 0 || reg_vol == 1)
146 vol = (reg_vol - 0) * 100000 + 1200000;
147 else if (reg_vol == 2 || reg_vol == 3)
148 vol = (reg_vol - 2) * 200000 + 1500000;
149 else if (reg_vol == 4 || reg_vol == 5)
150 vol = (reg_vol - 4) * 200000 + 1800000;
151 else if (reg_vol >= 6 && reg_vol <= 12)
152 vol = (reg_vol - 6) * 100000 + 2500000;
153 else if (reg_vol >= 13 && reg_vol <= 15)
154 vol = (reg_vol - 13) * 100000 + 3300000;
155 else
156 die("ERROR: Unknown vsim1 reg_vol %x", reg_vol);
158 printk(BIOS_INFO, "%s: reg_vol 0x%x, reg_cali 0x%x, vol %d, %d\n",
159 __func__, reg_vol, reg_cali, vol, (vol + reg_cali * 1000));
161 return (vol + reg_cali * 1000);
164 void mt6373_set_vcn33_3_voltage(u32 vcn33_3_uv)
166 udelay(100);
167 printk(BIOS_INFO, "%s start\n", __func__);
168 u32 reg_vol, reg_cali;
170 assert(pmif_arb);
172 if (vcn33_3_uv >= 1200000 && vcn33_3_uv <= 1300000)
173 reg_vol = (vcn33_3_uv - 1200000) / 100000;
174 else if (vcn33_3_uv >= 1500000 && vcn33_3_uv <= 1700000)
175 reg_vol = (vcn33_3_uv - 1500000) / 200000 + 2;
176 else if (vcn33_3_uv >= 1800000 && vcn33_3_uv <= 2000000)
177 reg_vol = (vcn33_3_uv - 1800000) / 200000 + 4;
178 else if (vcn33_3_uv >= 2500000 && vcn33_3_uv <= 3100000)
179 reg_vol = (vcn33_3_uv - 2500000) / 100000 + 6;
180 else if (vcn33_3_uv >= 3300000 && vcn33_3_uv <= 3500000)
181 reg_vol = (vcn33_3_uv - 3300000) / 100000 + 13;
182 else
183 die("ERROR: Unknown vcn33_3_uv voltage %u", vcn33_3_uv);
185 reg_cali = ((vcn33_3_uv / 1000) % 100) / 10;
187 mt6373_write8(MT6373_VCN33_3_ANA_CON1, reg_vol);
188 udelay(100);
189 mt6373_write8(MT6373_VCN33_3_ANA_CON0, reg_cali);
190 udelay(100);
191 printk(BIOS_INFO, "%s: 0x%x, %d\n", __func__, reg_vol, vcn33_3_uv);
194 void mt6373_enable_vcn33_3(bool enable)
196 mt6373_write_field(MT6373_LDO_VCN33_3_CON0, enable, 0x1, 0);
199 void mt6373_enable_vmc(bool enable)
201 mt6373_write_field(MT6373_LDO_VMC_CON0, enable, 0x1, 0);
204 void mt6373_enable_vmch(bool enable)
206 mt6373_write_field(MT6373_LDO_VMCH_CON0, enable, 0x1, 0);
209 void mt6373_enable_vant18(bool enable)
211 mt6373_write_field(MT6373_LDO_VANT18_CON0, enable, 0x1, 0);
214 void mt6373_enable_vsim1(bool enable)
216 mt6373_write_field(MT6373_LDO_VSIM1_CON0, enable, 0x1, 0);
219 void mt6373_enable_vsim2(bool enable)
221 mt6373_write_field(MT6373_LDO_VSIM2_CON0, enable, 0x1, 0);
224 static void mt6373_pmic_wdt_set(void)
226 /* [5]=1, RG_WDTRSTB_DEB */
227 mt6373_write_field(0x13a, 0x20, 0xFF, 0);
228 /* [1]=0, RG_WDTRSTB_MODE */
229 mt6373_write_field(0x13b, 0x02, 0xFF, 0);
230 /* [0]=1, RG_WDTRSTB_EN */
231 mt6373_write_field(0x13a, 0x01, 0xFF, 0);
232 /* Enable BUCK/LDO WDT VOSEL Debug */
233 mt6373_write_field(0x231, 0x1, 0x1, 0);
234 /* Clear WDT status */
235 mt6373_write_field(0x13a, 0x1, 0x1, 3);
236 udelay(50);
237 mt6373_write_field(0x13b, 0x1, 0x1, 3);
238 printk(BIOS_INFO, "[%s]WDTRSTB[0x139]=0x%x\n", __func__,
239 mt6373_read_field(0x139, 0xFF, 0));
242 void mt6373_init_pmif_arb(void)
244 if (!pmif_arb) {
245 pmif_arb = get_pmif_controller(PMIF_SPMI, SPMI_MASTER_1);
246 assert(pmif_arb);
249 if (pmif_arb->is_pmif_init_done(pmif_arb))
250 die("%s: initialization failed", __func__);
252 printk(BIOS_INFO, "[%s][MT6373]CHIP ID = 0x%x\n",
253 __func__, mt6373_read_field(MT6373_SWCID1, 0xFF, 0));
256 void mt6373_init(void)
258 printk(BIOS_INFO, "%s start\n", __func__);
259 mt6373_init_pmif_arb();
260 mt6373_pmic_wdt_set();
261 pmic_protect_key_setting(false);
262 mt6373_init_setting();
263 pmic_protect_key_setting(true);