src/soc/mediatek/mt8173/ddp.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <edid.h>
   5 #include <soc/addressmap.h>
   6 #include <soc/ddp.h>
   7 #include <types.h>
   8
   9 static void disp_config_main_path_connection(void)
  10 {
  11         write32(&mmsys_cfg->disp_ovl0_mout_en, OVL0_MOUT_EN_COLOR0);
  12         write32(&mmsys_cfg->disp_color0_sel_in, COLOR0_SEL_IN_OVL0);
  13         write32(&mmsys_cfg->disp_od_mout_en, OD_MOUT_EN_RDMA0);
  14         write32(&mmsys_cfg->disp_ufoe_mout_en, UFOE_MOUT_EN_DSI0);
  15         write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_UFOE);
  16 }
  17
  18 static void disp_config_main_path_mutex(void)
  19 {
  20         write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH);
  21
  22         /* Clock source from DSI0 */
  23         write32(&disp_mutex->mutex[0].sof, BIT(0));
  24         write32(&disp_mutex->mutex[0].en, BIT(0));
  25 }
  26
  27 static void od_start(u32 width, u32 height)
  28 {
  29         write32(&disp_od->size, width << 16 | height);
  30         write32(&disp_od->cfg, OD_RELAY_MODE);
  31
  32         write32(&disp_od->en, 1);
  33 }
  34
  35 static void main_disp_path_setup(u32 width, u32 height, u32 pixel_clk)
  36 {
  37         ovl_set_roi(0, width, height, 0);
  38         rdma_config(width, height, pixel_clk, 8 * KiB);
  39         od_start(width, height);
  40         write32(&disp_ufoe->start, UFO_BYPASS);
  41         color_start(width, height);
  42         disp_config_main_path_connection();
  43         disp_config_main_path_mutex();
  44 }
  45
  46 static void disp_clock_on(void)
  47 {
  48         clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_SMI_COMMON |
  49                                              CG_CON0_SMI_LARB0 |
  50                                              CG_CON0_MUTEX_32K |
  51                                              CG_CON0_DISP_OVL0 |
  52                                              CG_CON0_DISP_RDMA0 |
  53                                              CG_CON0_DISP_COLOR0 |
  54                                              CG_CON0_DISP_UFOE |
  55                                              CG_CON0_DISP_OD);
  56
  57         clrbits32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DSI0_ENGINE |
  58                                              CG_CON1_DSI0_DIGITAL);
  59 }
  60
  61 void mtk_ddp_init(void)
  62 {
  63         disp_clock_on();
  64 }
  65
  66 void mtk_ddp_mode_set(const struct edid *edid)
  67 {
  68         u32 fmt = OVL_INFMT_RGBA8888;
  69         u32 bpp = edid->framebuffer_bits_per_pixel / 8;
  70
  71         main_disp_path_setup(edid->mode.ha, edid->mode.va,
  72                              edid->mode.pixel_clock);
  73
  74         rdma_start();
  75         ovl_layer_config(fmt, bpp, edid->mode.ha, edid->mode.va);
  76 }