soc/intel/xeon_sp: Allow OS to control LTR and AER
[coreboot2.git] / src / soc / mediatek / mt8173 / gpio.c
blob8de8d0a1be9e18d1242680d27643efb88ffc4dc6
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 #include <device/mmio.h>
3 #include <assert.h>
4 #include <gpio.h>
5 #include <types.h>
7 enum {
8 MAX_GPIO_NUMBER = 134,
9 };
11 static void pos_bit_calc(gpio_t gpio, u32 *pos, u32 *bit)
13 *pos = gpio.id / MAX_GPIO_REG_BITS;
14 *bit = gpio.id % MAX_GPIO_REG_BITS;
17 void gpio_set_pull(gpio_t gpio, enum pull_enable enable,
18 enum pull_select select)
20 u32 pos;
21 u32 bit;
22 u32 *en_reg, *sel_reg;
23 u32 pin = gpio.id;
25 pos_bit_calc(gpio, &pos, &bit);
27 if (enable == GPIO_PULL_DISABLE) {
28 en_reg = &mtk_gpio->pullen[pos].rst;
29 } else {
30 /* These pins' pulls can't be set through GPIO controller. */
31 assert(pin < 22 || pin > 27);
32 assert(pin < 47 || pin > 56);
33 assert(pin < 57 || pin > 68);
34 assert(pin < 73 || pin > 78);
35 assert(pin < 100 || pin > 105);
36 assert(pin < 119 || pin > 124);
38 en_reg = &mtk_gpio->pullen[pos].set;
39 sel_reg = (select == GPIO_PULL_DOWN) ?
40 (&mtk_gpio->pullsel[pos].rst) :
41 (&mtk_gpio->pullsel[pos].set);
42 write16(sel_reg, 1L << bit);
44 write16(en_reg, 1L << bit);