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soc/intel/xeon_sp: Allow OS to control LTR and AER
[coreboot2.git] / src / soc / mediatek / mt8186 / pll.c
blob6b9eae67d87eae9ef7941a452da51ca7067314d5
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 /*
4 * This file is created based on MT8186 Functional Specification
5 * Chapter number: 3.2
6 */
7
8 #include <console/console.h>
9 #include <device/mmio.h>
10 #include <delay.h>
11 #include <timer.h>
12
13 #include <soc/addressmap.h>
14 #include <soc/infracfg.h>
15 #include <soc/mcucfg.h>
16 #include <soc/pll.h>
17
18 enum mux_id {
19 TOP_AXI_SEL,
20 TOP_SCP_SEL,
21 TOP_MFG_SEL,
22 TOP_CAMTG_SEL,
23 TOP_CAMTG1_SEL,
24 TOP_CAMTG2_SEL,
25 TOP_CAMTG3_SEL,
26 TOP_CAMTG4_SEL,
27 TOP_CAMTG5_SEL,
28 TOP_CAMTG6_SEL,
29 TOP_UART_SEL,
30 TOP_SPI_SEL,
31 TOP_MSDC50_0_HCLK_SEL,
32 TOP_MSDC50_0_SEL,
33 TOP_MSDC30_1_SEL,
34 TOP_AUDIO_SEL,
35 TOP_AUD_INTBUS_SEL,
36 TOP_AUD_1_SEL,
37 TOP_AUD_2_SEL,
38 TOP_AUD_ENGEN1_SEL,
39 TOP_AUD_ENGEN2_SEL,
40 TOP_DISP_PWM_SEL,
41 TOP_SSPM_SEL,
42 TOP_DXCC_SEL,
43 TOP_USB_TOP_SEL,
44 TOP_SRCK_SEL,
45 TOP_SPM_SEL,
46 TOP_I2C_SEL,
47 TOP_PWM_SEL,
48 TOP_SENINF_SEL,
49 TOP_SENINF1_SEL,
50 TOP_SENINF2_SEL,
51 TOP_SENINF3_SEL,
52 TOP_AES_MSDCFDE_SEL,
53 TOP_PWRAP_ULPOSC_SEL,
54 TOP_CAMTM_SEL,
55 TOP_VENC_SEL,
56 TOP_CAM_SEL,
57 TOP_IMG1_SEL,
58 TOP_IPE_SEL,
59 TOP_DPMAIF_SEL,
60 TOP_VDEC_SEL,
61 TOP_DISP_SEL,
62 TOP_MDP_SEL,
63 TOP_AUDIO_H_SEL,
64 TOP_UFS_SEL,
65 TOP_AES_FDE_SEL,
66 TOP_AUDIODSP_SEL,
67 TOP_DVFSRC_SEL,
68 TOP_DSI_OCC_SEL,
69 TOP_SPMI_MST_SEL,
70 TOP_SPINOR_SEL,
71 TOP_NNA_SEL,
72 TOP_NNA1_SEL,
73 TOP_NNA2_SEL,
74 TOP_SSUSB_XHCI_SEL,
75 TOP_SSUSB_TOP_1P_SEL,
76 TOP_SSUSB_XHCI_1P_SEL,
77 TOP_WPE_SEL,
78 TOP_MEM_SEL,
79 TOP_DPI_SEL,
80 TOP_U3_OCC_250M_SEL,
81 TOP_U3_OCC_500M_SEL,
82 TOP_ADSP_BUS_SEL,
83 TOP_NR_MUX
84 };
85
86 #define MUX(_id, _reg, _mux_shift, _mux_width) \
87 [_id] = { \
88 .reg = &mtk_topckgen->_reg, \
89 .mux_shift = _mux_shift, \
90 .mux_width = _mux_width, \
91 }
92
93 #define MUX_UPD(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\
94 [_id] = { \
95 .reg = &mtk_topckgen->_reg, \
96 .set_reg = &mtk_topckgen->_reg##_set, \
97 .clr_reg = &mtk_topckgen->_reg##_clr, \
98 .mux_shift = _mux_shift, \
99 .mux_width = _mux_width, \
100 .upd_reg = &mtk_topckgen->_upd_reg, \
101 .upd_shift = _upd_shift, \
102 }
103
104 static const struct mux muxes[] = {
105 /* CLK_CFG_0 */
106 MUX_UPD(TOP_AXI_SEL, clk_cfg_0, 0, 2, clk_cfg_update, 0),
107 MUX_UPD(TOP_SCP_SEL, clk_cfg_0, 8, 3, clk_cfg_update, 1),
108 MUX_UPD(TOP_MFG_SEL, clk_cfg_0, 16, 2, clk_cfg_update, 2),
109 MUX_UPD(TOP_CAMTG_SEL, clk_cfg_0, 24, 3, clk_cfg_update, 3),
110 /* CLK_CFG_1 */
111 MUX_UPD(TOP_CAMTG1_SEL, clk_cfg_1, 0, 3, clk_cfg_update, 4),
112 MUX_UPD(TOP_CAMTG2_SEL, clk_cfg_1, 8, 3, clk_cfg_update, 5),
113 MUX_UPD(TOP_CAMTG3_SEL, clk_cfg_1, 16, 3, clk_cfg_update, 6),
114 MUX_UPD(TOP_CAMTG4_SEL, clk_cfg_1, 24, 3, clk_cfg_update, 7),
115 /* CLK_CFG_2 */
116 MUX_UPD(TOP_CAMTG5_SEL, clk_cfg_2, 0, 3, clk_cfg_update, 8),
117 MUX_UPD(TOP_CAMTG6_SEL, clk_cfg_2, 8, 3, clk_cfg_update, 9),
118 MUX_UPD(TOP_UART_SEL, clk_cfg_2, 16, 1, clk_cfg_update, 10),
119 MUX_UPD(TOP_SPI_SEL, clk_cfg_2, 24, 3, clk_cfg_update, 11),
120 /* CLK_CFG_3 */
121 MUX_UPD(TOP_MSDC50_0_HCLK_SEL, clk_cfg_3, 0, 2, clk_cfg_update, 12),
122 MUX_UPD(TOP_MSDC50_0_SEL, clk_cfg_3, 8, 3, clk_cfg_update, 13),
123 MUX_UPD(TOP_MSDC30_1_SEL, clk_cfg_3, 16, 3, clk_cfg_update, 14),
124 MUX_UPD(TOP_AUDIO_SEL, clk_cfg_3, 24, 2, clk_cfg_update, 15),
125 /* CLK_CFG_4 */
126 MUX_UPD(TOP_AUD_INTBUS_SEL, clk_cfg_4, 0, 2, clk_cfg_update, 16),
127 MUX_UPD(TOP_AUD_1_SEL, clk_cfg_4, 8, 1, clk_cfg_update, 17),
128 MUX_UPD(TOP_AUD_2_SEL, clk_cfg_4, 16, 1, clk_cfg_update, 18),
129 MUX_UPD(TOP_AUD_ENGEN1_SEL, clk_cfg_4, 24, 2, clk_cfg_update, 19),
130 /* CLK_CFG_5 */
131 MUX_UPD(TOP_AUD_ENGEN2_SEL, clk_cfg_5, 0, 2, clk_cfg_update, 20),
132 MUX_UPD(TOP_DISP_PWM_SEL, clk_cfg_5, 8, 3, clk_cfg_update, 21),
133 MUX_UPD(TOP_SSPM_SEL, clk_cfg_5, 16, 3, clk_cfg_update, 22),
134 MUX_UPD(TOP_DXCC_SEL, clk_cfg_5, 24, 2, clk_cfg_update, 23),
135 /* CLK_CFG_6 */
136 MUX_UPD(TOP_USB_TOP_SEL, clk_cfg_6, 0, 2, clk_cfg_update, 24),
137 MUX_UPD(TOP_SRCK_SEL, clk_cfg_6, 8, 2, clk_cfg_update, 25),
138 MUX_UPD(TOP_SPM_SEL, clk_cfg_6, 16, 2, clk_cfg_update, 26),
139 MUX_UPD(TOP_I2C_SEL, clk_cfg_6, 24, 2, clk_cfg_update, 27),
140 /* CLK_CFG_7 */
141 MUX_UPD(TOP_PWM_SEL, clk_cfg_7, 0, 2, clk_cfg_update, 28),
142 MUX_UPD(TOP_SENINF_SEL, clk_cfg_7, 8, 2, clk_cfg_update, 29),
143 MUX_UPD(TOP_SENINF1_SEL, clk_cfg_7, 16, 2, clk_cfg_update, 30),
144 MUX_UPD(TOP_SENINF2_SEL, clk_cfg_7, 24, 2, clk_cfg_update1, 0),
145 /* CLK_CFG_8 */
146 MUX_UPD(TOP_SENINF3_SEL, clk_cfg_8, 0, 2, clk_cfg_update1, 1),
147 MUX_UPD(TOP_AES_MSDCFDE_SEL, clk_cfg_8, 8, 3, clk_cfg_update1, 2),
148 MUX_UPD(TOP_PWRAP_ULPOSC_SEL, clk_cfg_8, 16, 3, clk_cfg_update1, 3),
149 MUX_UPD(TOP_CAMTM_SEL, clk_cfg_8, 24, 2, clk_cfg_update1, 4),
150 /* CLK_CFG_9 */
151 MUX_UPD(TOP_VENC_SEL, clk_cfg_9, 0, 3, clk_cfg_update1, 5),
152 MUX_UPD(TOP_CAM_SEL, clk_cfg_9, 8, 4, clk_cfg_update1, 6),
153 MUX_UPD(TOP_IMG1_SEL, clk_cfg_9, 16, 4, clk_cfg_update1, 7),
154 MUX_UPD(TOP_IPE_SEL, clk_cfg_9, 24, 4, clk_cfg_update1, 8),
155 /* CLK_CFG_10 */
156 MUX_UPD(TOP_DPMAIF_SEL, clk_cfg_10, 0, 3, clk_cfg_update1, 9),
157 MUX_UPD(TOP_VDEC_SEL, clk_cfg_10, 8, 3, clk_cfg_update1, 10),
158 MUX_UPD(TOP_DISP_SEL, clk_cfg_10, 16, 4, clk_cfg_update1, 11),
159 MUX_UPD(TOP_MDP_SEL, clk_cfg_10, 24, 4, clk_cfg_update1, 12),
160 /* CLK_CFG_11 */
161 MUX_UPD(TOP_AUDIO_H_SEL, clk_cfg_11, 0, 2, clk_cfg_update1, 13),
162 MUX_UPD(TOP_UFS_SEL, clk_cfg_11, 8, 2, clk_cfg_update1, 14),
163 MUX_UPD(TOP_AES_FDE_SEL, clk_cfg_11, 16, 2, clk_cfg_update1, 15),
164 MUX_UPD(TOP_AUDIODSP_SEL, clk_cfg_11, 24, 3, clk_cfg_update1, 16),
165 /* CLK_CFG_12 */
166 MUX_UPD(TOP_DSI_OCC_SEL, clk_cfg_12, 8, 2, clk_cfg_update1, 18),
167 MUX_UPD(TOP_SPMI_MST_SEL, clk_cfg_12, 16, 3, clk_cfg_update1, 19),
168 /* CLK_CFG_13 */
169 MUX_UPD(TOP_SPINOR_SEL, clk_cfg_13, 0, 3, clk_cfg_update1, 20),
170 MUX_UPD(TOP_NNA_SEL, clk_cfg_13, 7, 4, clk_cfg_update1, 21),
171 MUX_UPD(TOP_NNA1_SEL, clk_cfg_13, 15, 4, clk_cfg_update1, 22),
172 MUX_UPD(TOP_NNA2_SEL, clk_cfg_13, 23, 4, clk_cfg_update1, 23),
173 /* CLK_CFG_14 */
174 MUX_UPD(TOP_SSUSB_XHCI_SEL, clk_cfg_14, 0, 2, clk_cfg_update1, 24),
175 MUX_UPD(TOP_SSUSB_TOP_1P_SEL, clk_cfg_14, 6, 2, clk_cfg_update1, 25),
176 MUX_UPD(TOP_SSUSB_XHCI_1P_SEL, clk_cfg_14, 12, 2, clk_cfg_update1, 26),
177 MUX_UPD(TOP_WPE_SEL, clk_cfg_14, 18, 4, clk_cfg_update1, 27),
178 /* CLK_CFG_15 */
179 MUX_UPD(TOP_DPI_SEL, clk_cfg_15, 0, 3, clk_cfg_update1, 28),
180 MUX_UPD(TOP_U3_OCC_250M_SEL, clk_cfg_15, 7, 1, clk_cfg_update1, 29),
181 MUX_UPD(TOP_U3_OCC_500M_SEL, clk_cfg_15, 12, 1, clk_cfg_update1, 30),
182 MUX_UPD(TOP_ADSP_BUS_SEL, clk_cfg_15, 17, 3, clk_cfg_update1, 31),
183 };
184
185 struct mux_sel {
186 enum mux_id id;
187 u32 sel;
188 };
189
190 static const struct mux_sel mux_sels[] = {
191 /* CLK_CFG_0 */
192 { .id = TOP_AXI_SEL, .sel = 1 }, /* 1: mainpll_d7 */
193 { .id = TOP_SCP_SEL, .sel = 3 }, /* 3: mainpll_d2_d2 */
194 { .id = TOP_MFG_SEL, .sel = 1 }, /* 1: mfgpll_ck */
195 { .id = TOP_CAMTG_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */
196 /* CLK_CFG_1 */
197 { .id = TOP_CAMTG1_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */
198 { .id = TOP_CAMTG2_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */
199 { .id = TOP_CAMTG3_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */
200 { .id = TOP_CAMTG4_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */
201 /* CLK_CFG_2 */
202 { .id = TOP_CAMTG5_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */
203 { .id = TOP_CAMTG6_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */
204 { .id = TOP_UART_SEL, .sel = 0 }, /* 0: clk26m */
205 { .id = TOP_SPI_SEL, .sel = 7 }, /* 7: mainpll_d5 */
206 /* CLK_CFG_3 */
207 { .id = TOP_MSDC50_0_HCLK_SEL, .sel = 1 }, /* 1: mainpll_d2_d2 */
208 { .id = TOP_MSDC50_0_SEL, .sel = 1 }, /* 1: msdcpll_ck */
209 { .id = TOP_MSDC30_1_SEL, .sel = 1 }, /* 1: msdcpll_d2 */
210 { .id = TOP_AUDIO_SEL, .sel = 1 }, /* 1: mainpll_d5_d4 */
211 /* CLK_CFG_4 */
212 { .id = TOP_AUD_INTBUS_SEL, .sel = 1 }, /* 1: mainpll_d2_d4 */
213 { .id = TOP_AUD_1_SEL, .sel = 1 }, /* 1: apll1_ck */
214 { .id = TOP_AUD_2_SEL, .sel = 1 }, /* 1: apll2_ck */
215 { .id = TOP_AUD_ENGEN1_SEL, .sel = 3 }, /* 3: apll1_d8 */
216 /* CLK_CFG_5 */
217 { .id = TOP_AUD_ENGEN2_SEL, .sel = 3 }, /* 3: apll2_d8 */
218 { .id = TOP_DISP_PWM_SEL, .sel = 1 }, /* 1: univpll_d5_d2 */
219 { .id = TOP_SSPM_SEL, .sel = 1 }, /* 1: mainpll_d2_d2 */
220 { .id = TOP_DXCC_SEL, .sel = 1 }, /* 1: mainpll_d2_d2 */
221 /* CLK_CFG_6 */
222 { .id = TOP_USB_TOP_SEL, .sel = 2 }, /* 2: univpll_d5_d2 */
223 { .id = TOP_SRCK_SEL, .sel = 2 }, /* 2: ulposc1_d10 */
224 { .id = TOP_SPM_SEL, .sel = 3 }, /* 3: mainpll_d7_d2 */
225 { .id = TOP_I2C_SEL, .sel = 3 }, /* 3: univpll_d5_d2 */
226 /* CLK_CFG_7 */
227 { .id = TOP_PWM_SEL, .sel = 3 }, /* 3: univpll_d2_d4 */
228 { .id = TOP_SENINF_SEL, .sel = 3 }, /* 3: univpll_d3_d2 */
229 { .id = TOP_SENINF1_SEL, .sel = 3 }, /* 3: univpll_d3_d2 */
230 { .id = TOP_SENINF2_SEL, .sel = 3 }, /* 3: univpll_d3_d2 */
231 /* CLK_CFG_8 */
232 { .id = TOP_SENINF3_SEL, .sel = 3 }, /* 3: univpll_d3_d2 */
233 { .id = TOP_AES_MSDCFDE_SEL, .sel = 1 }, /* 1: univpll_d3 */
234 { .id = TOP_PWRAP_ULPOSC_SEL, .sel = 0 }, /* 0: clk26m */
235 { .id = TOP_CAMTM_SEL, .sel = 2 }, /* 2: univpll_d3_d2 */
236 /* CLK_CFG_9 */
237 { .id = TOP_VENC_SEL, .sel = 6 }, /* 6: mainpll_d3 */
238 { .id = TOP_CAM_SEL, .sel = 7 }, /* 7: univpll_d2_d2 */
239 { .id = TOP_IMG1_SEL, .sel = 7 }, /* 7: univpll_d2_d2 */
240 { .id = TOP_IPE_SEL, .sel = 7 }, /* 7: univpll_d2_d2 */
241 /* CLK_CFG_10 */
242 { .id = TOP_DPMAIF_SEL, .sel = 1 }, /* 1: univpll_d2_d2 */
243 { .id = TOP_VDEC_SEL, .sel = 6 }, /* 6: univpll_d2_d2 */
244 { .id = TOP_DISP_SEL, .sel = 8 }, /* 8: mmpll_ck */
245 { .id = TOP_MDP_SEL, .sel = 8 }, /* 8: mmpll_ck */
246 /* CLK_CFG_11 */
247 { .id = TOP_AUDIO_H_SEL, .sel = 3 }, /* 3: apll2_ck */
248 { .id = TOP_UFS_SEL, .sel = 1 }, /* 1: mainpll_d7 */
249 { .id = TOP_AES_FDE_SEL, .sel = 1 }, /* 1: univpll_d3 */
250 { .id = TOP_AUDIODSP_SEL, .sel = 0 }, /* 0: clk26m */
251 /* CLK_CFG_12 */
252 { .id = TOP_DSI_OCC_SEL, .sel = 1 }, /* 1: univpll_d3_d2 */
253 { .id = TOP_SPMI_MST_SEL, .sel = 2 }, /* 2: ulposc1_d4 */
254 /* CLK_CFG_13 */
255 { .id = TOP_SPINOR_SEL, .sel = 3 }, /* 3: univpll_d3_d8 */
256 { .id = TOP_NNA_SEL, .sel = 14 }, /* 14: nnapll_ck */
257 { .id = TOP_NNA1_SEL, .sel = 14 }, /* 14: nnapll_ck */
258 { .id = TOP_NNA2_SEL, .sel = 15 }, /* 15: nna2pll_ck */
259 /* CLK_CFG_14 */
260 { .id = TOP_SSUSB_XHCI_SEL, .sel = 2 }, /* 2: univpll_d5_d2 */
261 { .id = TOP_SSUSB_TOP_1P_SEL, .sel = 2 }, /* 2: univpll_d5_d2 */
262 { .id = TOP_SSUSB_XHCI_1P_SEL, .sel = 2 }, /* 2: univpll_d5_d2 */
263 { .id = TOP_WPE_SEL, .sel = 8 }, /* 8: mmpll_ck */
264 /* CLK_CFG_15 */
265 { .id = TOP_DPI_SEL, .sel = 1 }, /* 1: tvdpll_ck */
266 { .id = TOP_U3_OCC_250M_SEL, .sel = 1 }, /* 1: univpll_d5 */
267 { .id = TOP_U3_OCC_500M_SEL, .sel = 1 }, /* 1: nna2pll_d2 */
268 { .id = TOP_ADSP_BUS_SEL, .sel = 3 }, /* 3: mainpll_d2_d2 */
269 };
270
271 enum pll_id {
272 APMIXED_ARMPLL_LL,
273 APMIXED_ARMPLL_BL,
274 APMIXED_CCIPLL,
275 APMIXED_MAINPLL,
276 APMIXED_UNIV2PLL,
277 APMIXED_MSDCPLL,
278 APMIXED_MMPLL,
279 APMIXED_NNAPLL,
280 APMIXED_NNA2PLL,
281 APMIXED_ADSPPLL,
282 APMIXED_MFGPLL,
283 APMIXED_TVDPLL,
284 APMIXED_APLL1,
285 APMIXED_APLL2,
286 APMIXED_PLL_MAX
287 };
288
289 static const u32 pll_div_rate[] = {
290 3800UL * MHz,
291 1900 * MHz,
292 950 * MHz,
293 475 * MHz,
294 237500 * KHz,
295 0,
296 };
297
298 static const struct pll plls[] = {
299 PLL(APMIXED_ARMPLL_LL, armpll_ll_con0, armpll_ll_con3,
300 NO_RSTB_SHIFT, 22, armpll_ll_con1, 24, armpll_ll_con1, 0,
301 pll_div_rate),
302 PLL(APMIXED_ARMPLL_BL, armpll_bl_con0, armpll_bl_con3,
303 NO_RSTB_SHIFT, 22, armpll_bl_con1, 24, armpll_bl_con1, 0,
304 pll_div_rate),
305 PLL(APMIXED_CCIPLL, ccipll_con0, ccipll_con3,
306 NO_RSTB_SHIFT, 22, ccipll_con1, 24, ccipll_con1, 0,
307 pll_div_rate),
308 PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_con3,
309 23, 22, mainpll_con1, 24, mainpll_con1, 0,
310 pll_div_rate),
311 PLL(APMIXED_UNIV2PLL, univpll_con0, univpll_con3,
312 23, 22, univpll_con1, 24, univpll_con1, 0,
313 pll_div_rate),
314 PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_con3,
315 NO_RSTB_SHIFT, 22, msdcpll_con1, 24, msdcpll_con1, 0,
316 pll_div_rate),
317 PLL(APMIXED_MMPLL, mmpll_con0, mmpll_con3,
318 NO_RSTB_SHIFT, 22, mmpll_con1, 24, mmpll_con1, 0,
319 pll_div_rate),
320 PLL(APMIXED_NNAPLL, nnapll_con0, nnapll_con3,
321 NO_RSTB_SHIFT, 22, nnapll_con1, 24, nnapll_con1, 0,
322 pll_div_rate),
323 PLL(APMIXED_NNA2PLL, nna2pll_con0, nna2pll_con3,
324 NO_RSTB_SHIFT, 22, nna2pll_con1, 24, nna2pll_con1, 0,
325 pll_div_rate),
326 PLL(APMIXED_ADSPPLL, adsppll_con0, adsppll_con3,
327 NO_RSTB_SHIFT, 22, adsppll_con1, 24, adsppll_con1, 0,
328 pll_div_rate),
329 PLL(APMIXED_MFGPLL, mfgpll_con0, mfgpll_con3,
330 NO_RSTB_SHIFT, 22, mfgpll_con1, 24, mfgpll_con1, 0,
331 pll_div_rate),
332 PLL(APMIXED_TVDPLL, tvdpll_con0, tvdpll_con3,
333 NO_RSTB_SHIFT, 22, tvdpll_con1, 24, tvdpll_con1, 0,
334 pll_div_rate),
335 PLL(APMIXED_APLL1, apll1_con0, apll1_con4,
336 NO_RSTB_SHIFT, 32, apll1_con1, 24, apll1_con2, 0,
337 pll_div_rate),
338 PLL(APMIXED_APLL2, apll2_con0, apll2_con4,
339 NO_RSTB_SHIFT, 32, apll2_con1, 24, apll2_con2, 0,
340 pll_div_rate),
341 };
342
343 struct rate {
344 enum pll_id id;
345 u32 rate;
346 };
347
348 static const struct rate rates[] = {
349 { .id = APMIXED_ARMPLL_LL, .rate = ARMPLL_LL_HZ },
350 { .id = APMIXED_ARMPLL_BL, .rate = ARMPLL_BL_HZ },
351 { .id = APMIXED_CCIPLL, .rate = CCIPLL_HZ },
352 { .id = APMIXED_MAINPLL, .rate = MAINPLL_HZ },
353 { .id = APMIXED_UNIV2PLL, .rate = UNIV2PLL_HZ },
354 { .id = APMIXED_MSDCPLL, .rate = MSDCPLL_HZ },
355 { .id = APMIXED_MMPLL, .rate = MMPLL_HZ },
356 { .id = APMIXED_NNAPLL, .rate = NNAPLL_HZ },
357 { .id = APMIXED_NNA2PLL, .rate = NNA2PLL_HZ },
358 { .id = APMIXED_ADSPPLL, .rate = ADSPPLL_HZ },
359 { .id = APMIXED_MFGPLL, .rate = MFGPLL_HZ },
360 { .id = APMIXED_TVDPLL, .rate = TVDPLL_HZ },
361 { .id = APMIXED_APLL1, .rate = APLL1_HZ },
362 { .id = APMIXED_APLL2, .rate = APLL2_HZ },
363 };
364
365 void pll_set_pcw_change(const struct pll *pll)
366 {
367 setbits32(pll->div_reg, PLL_PCW_CHG);
368 }
369
370 void mt_pll_init(void)
371 {
372 int i;
373
374 /* enable clock square */
375 setbits32(&mtk_apmixed->ap_pll_con0, BIT(0));
376
377 udelay(PLL_CKSQ_ON_DELAY);
378
379 /* enable clock square1 low-pass filter */
380 setbits32(&mtk_apmixed->ap_pll_con0, BIT(1));
381
382 /* xPLL PWR ON */
383 for (i = 0; i < APMIXED_PLL_MAX; i++)
384 setbits32(plls[i].pwr_reg, PLL_PWR_ON);
385
386 udelay(PLL_PWR_ON_DELAY);
387
388 /* xPLL ISO Disable */
389 for (i = 0; i < APMIXED_PLL_MAX; i++)
390 clrbits32(plls[i].pwr_reg, PLL_ISO);
391
392 udelay(PLL_ISO_DELAY);
393
394 /* disable glitch free if rate < 374MHz */
395 for (i = 0; i < ARRAY_SIZE(rates); i++) {
396 if (rates[i].rate < 374 * MHz)
397 clrbits32(plls[rates[i].id].reg, GLITCH_FREE_EN);
398 }
399
400 /* xPLL Frequency Set */
401 for (i = 0; i < ARRAY_SIZE(rates); i++)
402 pll_set_rate(&plls[rates[i].id], rates[i].rate);
403
404 /* AUDPLL Tuner Frequency Set */
405 write32(&mtk_apmixed->apll1_tuner_con0, read32(&mtk_apmixed->apll1_con2) + 1);
406 write32(&mtk_apmixed->apll2_tuner_con0, read32(&mtk_apmixed->apll2_con2) + 1);
407
408 /* xPLL Frequency Enable */
409 for (i = 0; i < APMIXED_PLL_MAX; i++)
410 setbits32(plls[i].reg, MT8186_PLL_EN);
411
412 /* wait for PLL stable */
413 udelay(PLL_EN_DELAY);
414
415 /* xPLL DIV Enable & RSTB */
416 for (i = 0; i < APMIXED_PLL_MAX; i++) {
417 if (plls[i].rstb_shift != NO_RSTB_SHIFT) {
418 setbits32(plls[i].reg, PLL_DIV_EN);
419 setbits32(plls[i].reg, 1 << plls[i].rstb_shift);
420 }
421 }
422
423 /* MCUCFG CLKMUX */
424 setbits32(&mtk_topckgen->clk_misc_cfg_0, ARMPLL_DIVIDER_PLL1_EN);
425 setbits32(&mtk_topckgen->clk_misc_cfg_0, ARMPLL_DIVIDER_PLL2_EN);
426
427 clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1);
428 clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1);
429 clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1);
430
431 clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
432 clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
433 clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
434
435 write32(&mt8186_infracfg_ao->infra_bus_dcm_ctrl, 0x805f0603);
436 write32(&mt8186_infracfg_ao->peri_bus_dcm_ctrl, 0xb07f0603);
437
438 /* dcm_infracfg_ao_audio_bus and dcm_infracfg_ao_icusb_bus */
439 SET32_BITFIELDS(&mt8186_infracfg_ao->peri_bus_dcm_ctrl,
440 INFRACFG_AO_AUDIO_BUS_REG0, 0,
441 INFRACFG_AO_ICUSB_BUS_REG0, 0,
442 INFRACFG_AO_AUDIO_BUS_REG0, 1,
443 INFRACFG_AO_ICUSB_BUS_REG0, 1);
444
445 /* dcm_infracfg_ao_infra_bus */
446 SET32_BITFIELDS(&mt8186_infracfg_ao->infra_bus_dcm_ctrl,
447 INFRACFG_AO_INFRA_BUS_REG0_0, 0,
448 INFRACFG_AO_INFRA_BUS_REG0_1, 0,
449 INFRACFG_AO_INFRA_BUS_REG0_2, 0,
450 INFRACFG_AO_INFRA_BUS_REG0_0, 0x603,
451 INFRACFG_AO_INFRA_BUS_REG0_1, 0xF,
452 INFRACFG_AO_INFRA_BUS_REG0_2, 1);
453
454 /* dcm_infracfg_ao_p2p_rx_clk */
455 SET32_BITFIELDS(&mt8186_infracfg_ao->p2p_rx_clk_on,
456 INFRACFG_AO_P2P_RX_CLK_REG0_MASK_0, 0,
457 INFRACFG_AO_P2P_RX_CLK_REG0_MASK_1, 0,
458 INFRACFG_AO_P2P_RX_CLK_REG0_MASK_1, 1);
459
460 /* dcm_infracfg_ao_peri_bus */
461 SET32_BITFIELDS(&mt8186_infracfg_ao->peri_bus_dcm_ctrl,
462 INFRACFG_AO_PERI_BUS_REG0_0, 0,
463 INFRACFG_AO_PERI_BUS_REG0_1, 0,
464 INFRACFG_AO_PERI_BUS_REG0_2, 0,
465 INFRACFG_AO_PERI_BUS_REG0_0, 3,
466 INFRACFG_AO_PERI_BUS_REG0_1, 0xFF07C,
467 INFRACFG_AO_PERI_BUS_REG0_2, 1);
468
469 for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
470 pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
471
472 /* [4] SCP_CORE_CK_CG, [5] SEJ_CG */
473 write32(&mt8186_infracfg_ao->module_sw_cg_0_clr, 0x00000030);
474 /* [7] DVFSRC_CG, [20] DEVICE_APC_CG */
475 write32(&mt8186_infracfg_ao->module_sw_cg_1_clr, 0x00100080);
476 /*
477 * [15] SEJ_F13M_CK_CG, [16] AES_TOP0_BCLK_CK_CG,
478 * [22] FADSP_26M_CG, [23] FADSP_32K_CG, [27] FADSP_CK_CG
479 */
480 write32(&mt8186_infracfg_ao->module_sw_cg_3_clr, 0x08C18000);
481 }
482
483 void mt_pll_raise_little_cpu_freq(u32 freq)
484 {
485 /* switch clock source to intermediate clock */
486 clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M);
487
488 /* disable armpll_ll frequency output */
489 clrbits32(plls[APMIXED_ARMPLL_LL].reg, MT8186_PLL_EN);
490
491 /* raise armpll_ll frequency */
492 pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq);
493
494 /* enable armpll_ll frequency output */
495 setbits32(plls[APMIXED_ARMPLL_LL].reg, MT8186_PLL_EN);
496 udelay(PLL_EN_DELAY);
497
498 /* switch clock source back to armpll_ll */
499 clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
500 }
501
502 void mt_pll_raise_cci_freq(u32 freq)
503 {
504 /* switch clock source to intermediate clock */
505 clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_26M);
506
507 /* disable ccipll frequency output */
508 clrbits32(plls[APMIXED_CCIPLL].reg, MT8186_PLL_EN);
509
510 /* raise ccipll frequency */
511 pll_set_rate(&plls[APMIXED_CCIPLL], freq);
512
513 /* enable ccipll frequency output */
514 setbits32(plls[APMIXED_CCIPLL].reg, MT8186_PLL_EN);
515 udelay(PLL_EN_DELAY);
516
517 /* switch clock source back to ccipll */
518 clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
519 }
520
521 void mt_pll_set_usb_clock(void)
522 {
523 /* enable usb macro control */
524 SET32_BITFIELDS(&mtk_topckgen->usb_top_cfg, USB_TOP_CFG_MACRO_CTRL, 3);
525 }
526
527 void mt_pll_spmi_mux_select(void)
528 {
529 /* 4: ulposc1_d10 */
530 pll_mux_set_sel(&muxes[TOP_SPMI_MST_SEL], 4);
531 }
532
533 u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)
534 {
535 u32 output, count, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_0, clk26cali_1;
536
537 /* backup */
538 clk_dbg_cfg = read32(&mtk_topckgen->clk_dbg_cfg);
539 clk_misc_cfg_0 = read32(&mtk_topckgen->clk_misc_cfg_0);
540 clk26cali_0 = read32(&mtk_topckgen->clk26cali_0);
541 clk26cali_1 = read32(&mtk_topckgen->clk26cali_1);
542
543 /* set up frequency meter */
544 if (type == FMETER_ABIST) {
545 SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg,
546 CLK_DBG_CFG_ABIST_CK_SEL, id,
547 CLK_DBG_CFG_CKGEN_CK_SEL, 0,
548 CLK_DBG_CFG_METER_CK_SEL, 0);
549 SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0,
550 CLK_MISC_CFG_0_METER_DIV, 1);
551 } else if (type == FMETER_CKGEN) {
552 SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg,
553 CLK_DBG_CFG_ABIST_CK_SEL, 0,
554 CLK_DBG_CFG_CKGEN_CK_SEL, id,
555 CLK_DBG_CFG_METER_CK_SEL, 1);
556 SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0,
557 CLK_MISC_CFG_0_METER_DIV, 0);
558 } else {
559 die("unsupported fmeter type\n");
560 }
561
562 /* enable frequency meter */
563 SET32_BITFIELDS(&mtk_topckgen->clk26cali_0, CLK26CALI_0_ENABLE, 1);
564
565 /* trigger frequency meter */
566 SET32_BITFIELDS(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER, 1);
567
568 /* wait frequency meter until finished */
569 if (wait_us(200, !READ32_BITFIELD(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER))) {
570 count = read32(&mtk_topckgen->clk26cali_1) & 0xffff;
571 output = (count * 26000) / 1024; /* KHz */
572 } else {
573 output = 0;
574 }
575
576 /* restore */
577 write32(&mtk_topckgen->clk_dbg_cfg, clk_dbg_cfg);
578 write32(&mtk_topckgen->clk_misc_cfg_0, clk_misc_cfg_0);
579 write32(&mtk_topckgen->clk26cali_0, clk26cali_0);
580 write32(&mtk_topckgen->clk26cali_1, clk26cali_1);
581
582 if (type == FMETER_ABIST)
583 return output * 2;
584 else if (type == FMETER_CKGEN)
585 return output;
586
587 return 0;
588 }
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