soc/intel/xeon_sp: Allow OS to control LTR and AER
[coreboot2.git] / src / soc / mediatek / mt8186 / pmif.c
blobc1a9bccc5ef332b35303006b00cceb9bdee9e5a6
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 /*
4 * This file is created based on MT8186 Functional Specification
5 * Chapter number: 3.7
6 */
8 #include <device/mmio.h>
9 #include <soc/pmif.h>
11 #define SLEEP_PROT_CTRL 0x3F0
13 DEFINE_BITFIELD(SPM_SLEEP_REQ_SEL, 1, 0)
14 DEFINE_BITFIELD(SCP_SLEEP_REQ_SEL, 10, 9)
16 void pmif_spmi_set_lp_mode(void)
18 SET32_BITFIELDS((void *)(PMIF_SPMI_BASE + SLEEP_PROT_CTRL),
19 SPM_SLEEP_REQ_SEL, 0,
20 SCP_SLEEP_REQ_SEL, 0);