src/soc/mediatek/mt8186/pmif_spmi.c

   1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
   2
   3 #include <device/mmio.h>
   4 #include <soc/pll.h>
   5 #include <soc/pmif_spmi.h>
   6
   7 /* IOCFG_LT, DRV_CFG2 */
   8 DEFINE_BITFIELD(SPMI_SCL, 14, 12)
   9 DEFINE_BITFIELD(SPMI_SDA, 17, 15)
  10 DEFINE_BIT(SPMI_SCL_IN, 27)
  11 DEFINE_BIT(SPMI_SDA_IN, 28)
  12 DEFINE_BIT(SPMI_SCL_PU, 11)
  13 DEFINE_BIT(SPMI_SDA_PD, 12)
  14 DEFINE_BIT(SPMI_SCL_SMT, 28)
  15 DEFINE_BIT(SPMI_SDA_SMT, 28)
  16 DEFINE_BITFIELD(SPMI_TD, 19, 16)
  17 DEFINE_BITFIELD(SPMI_RD, 15, 14)
  18 DEFINE_BITFIELD(SPMI_DRI, 5, 3)
  19
  20 /* TOPRGU, WDT_SWSYSRST2 */
  21 DEFINE_BIT(SPMI_MST_RST, 23)
  22 DEFINE_BITFIELD(UNLOCK_KEY, 31, 24)
  23
  24 /* TOPCKGEN, CLK_CFG_17 */
  25 DEFINE_BITFIELD(CLK_SPMI_MST_SEL, 10, 8)
  26 DEFINE_BIT(CLK_SPMI_MST_INT, 12)
  27 DEFINE_BIT(PDN_SPMI_MST, 15)
  28
  29 /* TOPCKGEN, CLK_CFG_UPDATE2 */
  30 DEFINE_BIT(SPMI_MST_CK_UPDATE, 5)
  31
  32 const struct spmi_device spmi_dev[] = {
  33         {
  34                 .slvid = SPMI_SLAVE_6,
  35                 .type = BUCK_CPU,
  36                 .type_id = BUCK_CPU_ID,
  37         },
  38 };
  39
  40 const size_t spmi_dev_cnt = ARRAY_SIZE(spmi_dev);
  41
  42 int spmi_config_master(void)
  43 {
  44         /* Software reset */
  45         SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 1, UNLOCK_KEY, 0x88);
  46
  47         SET32_BITFIELDS(&mtk_topckgen->clk_cfg_11,
  48                         CLK_SPMI_MST_SEL, 0x3,
  49                         CLK_SPMI_MST_INT, 0,
  50                         PDN_SPMI_MST, 0);
  51         SET32_BITFIELDS(&mtk_topckgen->clk_cfg_update2, SPMI_MST_CK_UPDATE, 1);
  52
  53         /* Software reset */
  54         SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 0, UNLOCK_KEY, 0x88);
  55
  56         /* Enable SPMI */
  57         write32(&mtk_spmi_mst->mst_req_en, 1);
  58         write32(&mtk_spmi_mst->rcs_ctrl, 0x15);
  59
  60         return 0;
  61 }