src/soc/mediatek/mt8186/rtc.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * This file is created based on MT8186 Functional Specification
   5  * Chapter number: 5.13
   6  */
   7
   8 #include <delay.h>
   9 #include <soc/rtc.h>
  10 #include <soc/rtc_common.h>
  11 #include <soc/mt6366.h>
  12 #include <soc/pmic_wrap.h>
  13 #include <timer.h>
  14
  15 #define MT8186_RTC_DXCO_CAPID 0xE0
  16
  17 /* Initialize RTC setting of using DCXO clock */
  18 static bool rtc_enable_dcxo(void)
  19 {
  20         u16 bbpu, con, osc32con, sec;
  21
  22         rtc_read(RTC_BBPU, &bbpu);
  23         rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
  24
  25         if (!rtc_write_trigger()) {
  26                 rtc_info("rtc_write_trigger() failed\n");
  27                 return false;
  28         }
  29
  30         mdelay(1);
  31         if (!rtc_writeif_unlock()) {
  32                 rtc_info("rtc_writeif_unlock() failed\n");
  33                 return false;
  34         }
  35
  36         rtc_read(RTC_OSC32CON, &osc32con);
  37         osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK
  38                       | RTC_GPS_CKOUT_EN);
  39         osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB
  40                     | RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION;
  41         if (!rtc_xosc_write(osc32con)) {
  42                 rtc_info("rtc_xosc_write() failed\n");
  43                 return false;
  44         }
  45
  46         rtc_read(RTC_CON, &con);
  47         rtc_read(RTC_OSC32CON, &osc32con);
  48         rtc_read(RTC_AL_SEC, &sec);
  49         rtc_info("con = %#x, osc32con = %#x, sec = %#x\n", con, osc32con, sec);
  50
  51         return true;
  52 }
  53
  54 /* Initialize RTC related gpio */
  55 bool rtc_gpio_init(void)
  56 {
  57         u16 con;
  58
  59         /* RTC_32K1V8 clock change from 128k div 4 source to RTC 32k source */
  60         pwrap_write_field(PMIC_RG_TOP_CKSEL_CON0_SET, 0x1, 0x1, 3);
  61
  62         /* Export 32K clock RTC_32K1V8_1 */
  63         pwrap_write_field(PMIC_RG_TOP_CKPDN_CON1_CLR, 0x1, 0x1, 1);
  64
  65         /* Export 32K clock RTC_32K2V8 */
  66         rtc_read(RTC_CON, &con);
  67         con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN
  68                 | RTC_CON_XOSC32_LPEN);
  69         con |= (RTC_CON_GPEN | RTC_CON_GOE);
  70         con &= ~RTC_CON_F32KOB;
  71         rtc_write(RTC_CON, con);
  72
  73         return rtc_write_trigger();
  74 }
  75
  76 u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size)
  77 {
  78         u16 bbpu, osc32con;
  79         u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel;
  80
  81         rtc_read(RTC_BBPU, &bbpu);
  82         rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
  83         if (!rtc_write_trigger()) {
  84                 rtc_info("rtc_write_trigger() failed\n");
  85                 return false;
  86         }
  87
  88         rtc_read(RTC_OSC32CON, &osc32con);
  89         if (!rtc_xosc_write((osc32con & ~RTC_XOSCCALI_MASK) |
  90                             (val & RTC_XOSCCALI_MASK))) {
  91                 rtc_info("rtc_xosc_write() failed\n");
  92                 return false;
  93         }
  94
  95         /* Enable FQMTR clock */
  96         pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1,
  97                           PMIC_RG_FQMTR_32K_CK_PDN_SHIFT);
  98         pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1,
  99                           PMIC_RG_FQMTR_CK_PDN_SHIFT);
 100
 101         /* FQMTR reset */
 102         pwrap_write_field(PMIC_RG_FQMTR_RST, 1, 1, PMIC_FQMTR_RST_SHIFT);
 103         do {
 104                 rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data);
 105                 rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy);
 106         } while (fqmtr_data && (fqmtr_busy & PMIC_FQMTR_CON0_BUSY));
 107         rtc_read(PMIC_RG_FQMTR_RST, &fqmtr_rst);
 108         /* FQMTR normal */
 109         pwrap_write_field(PMIC_RG_FQMTR_RST, 0, 1, PMIC_FQMTR_RST_SHIFT);
 110
 111         /* Set frequency meter window value (0=1X32K(fixed clock)) */
 112         rtc_write(PMIC_RG_FQMTR_WINSET, window_size);
 113         /* Enable 26M and set test clock source */
 114         rtc_write(PMIC_RG_FQMTR_CON0, PMIC_FQMTR_CON0_DCXO26M_EN | measure_src);
 115         /* Enable 26M -> delay 100us -> enable FQMTR */
 116         udelay(100);
 117         rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
 118         /* Enable FQMTR */
 119         rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel | PMIC_FQMTR_CON0_FQMTR_EN);
 120         udelay(100);
 121
 122         /* FQMTR read until ready */
 123         if (!wait_us(FQMTR_TIMEOUT_US,
 124                      rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy) == 0 &&
 125                      !(fqmtr_busy & PMIC_FQMTR_CON0_BUSY))) {
 126                 rtc_info("get frequency time out: %#x\n", fqmtr_busy);
 127                 return false;
 128         }
 129
 130         /* Read data should be closed to 26M/32k = 794 */
 131         rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data);
 132
 133         rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
 134         /* Disable FQMTR */
 135         rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel & ~PMIC_FQMTR_CON0_FQMTR_EN);
 136         /* Disable FQMTR -> delay 100us -> disable 26M */
 137         udelay(100);
 138         /* Disable 26M */
 139         rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
 140         rtc_write(PMIC_RG_FQMTR_CON0,
 141                   fqmtr_tcksel & ~PMIC_FQMTR_CON0_DCXO26M_EN);
 142         rtc_info("input = %#x, output = %#x\n", val, fqmtr_data);
 143
 144         /* Disable FQMTR clock */
 145         pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1,
 146                           PMIC_RG_FQMTR_32K_CK_PDN_SHIFT);
 147         pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1,
 148                           PMIC_RG_FQMTR_CK_PDN_SHIFT);
 149
 150         return fqmtr_data;
 151 }
 152
 153 /* Low power detect setting */
 154 static bool rtc_lpd_init(void)
 155 {
 156         u16 con, sec;
 157
 158         /* Set RTC_LPD_OPT */
 159         rtc_read(RTC_AL_SEC, &sec);
 160         sec |= RTC_LPD_OPT_F32K_CK_ALIVE;
 161         rtc_write(RTC_AL_SEC, sec);
 162         if (!rtc_write_trigger()) {
 163                 rtc_info("rtc_write_trigger() failed\n");
 164                 return false;
 165         }
 166
 167         /* Initialize XOSC32 to detect 32k clock stop */
 168         rtc_read(RTC_CON, &con);
 169         con |= RTC_CON_XOSC32_LPEN;
 170         if (!rtc_lpen(con))
 171                 return false;
 172
 173         /* Initialize EOSC32 to detect RTC low power */
 174         rtc_read(RTC_CON, &con);
 175         con |= RTC_CON_EOSC32_LPEN;
 176         if (!rtc_lpen(con))
 177                 return false;
 178
 179         rtc_read(RTC_CON, &con);
 180         con &= ~RTC_CON_XOSC32_LPEN;
 181         rtc_write(RTC_CON, con);
 182
 183         /* Set RTC_LPD_OPT */
 184         rtc_read(RTC_AL_SEC, &sec);
 185         sec &= ~RTC_LPD_OPT_MASK;
 186         sec |= RTC_LPD_OPT_EOSC_LPD;
 187         rtc_write(RTC_AL_SEC, sec);
 188         if (!rtc_write_trigger()) {
 189                 rtc_info("rtc_write_trigger() failed\n");
 190                 return false;
 191         }
 192
 193         return true;
 194 }
 195
 196 static bool rtc_hw_init(void)
 197 {
 198         u16 bbpu;
 199
 200         rtc_read(RTC_BBPU, &bbpu);
 201         rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_INIT);
 202         if (!rtc_write_trigger()) {
 203                 rtc_info("rtc_write_trigger() failed\n");
 204                 return false;
 205         }
 206
 207         udelay(500);
 208
 209         rtc_read(RTC_BBPU, &bbpu);
 210         rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
 211         if (!rtc_write_trigger()) {
 212                 rtc_info("rtc_write_trigger() failed\n");
 213                 return false;
 214         }
 215
 216         rtc_read(RTC_BBPU, &bbpu);
 217         if (bbpu & RTC_BBPU_INIT) {
 218                 rtc_info("timeout\n");
 219                 return false;
 220         }
 221
 222         return true;
 223 }
 224
 225 static void mt6366_dcxo_disable_unused(void)
 226 {
 227         /* Disable clock buffer XO_CEL */
 228         rtc_write(PMIC_RG_DCXO_CW00_CLR, 0x0800);
 229         /* Mask bblpm request and switch off bblpm mode */
 230         rtc_write(PMIC_RG_DCXO_CW23, 0x0052);
 231 }
 232
 233 static void rtc_set_capid(u16 capid)
 234 {
 235         u16 read_capid;
 236
 237         rtc_write(PMIC_RG_DCXO_CW03, 0xFF00 | capid);
 238
 239         rtc_read(PMIC_RG_DCXO_CW03, &read_capid);
 240         rtc_info("read back capid: %#x\n", read_capid & 0xFF);
 241 }
 242
 243 /* Check RTC Initialization */
 244 int rtc_init(int recover)
 245 {
 246         int ret;
 247
 248         rtc_info("recovery: %d\n", recover);
 249
 250         /* Write powerkeys to enable RTC functions */
 251         if (!rtc_powerkey_init()) {
 252                 ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
 253                 goto err;
 254         }
 255
 256         /* Write interface unlock need to be set after powerkey match */
 257         if (!rtc_writeif_unlock()) {
 258                 ret = -RTC_STATUS_WRITEIF_UNLOCK_FAIL;
 259                 goto err;
 260         }
 261
 262         rtc_osc_init();
 263
 264         /* In recovery mode, we need 20ms delay for register setting. */
 265         if (recover)
 266                 mdelay(20);
 267
 268         if (!rtc_gpio_init()) {
 269                 ret = -RTC_STATUS_GPIO_INIT_FAIL;
 270                 goto err;
 271         }
 272
 273         if (!rtc_hw_init()) {
 274                 ret = -RTC_STATUS_HW_INIT_FAIL;
 275                 goto err;
 276         }
 277
 278         if (!rtc_reg_init()) {
 279                 ret = -RTC_STATUS_REG_INIT_FAIL;
 280                 goto err;
 281         }
 282
 283         if (!rtc_lpd_init()) {
 284                 ret = -RTC_STATUS_LPD_INIT_FAIL;
 285                 goto err;
 286         }
 287
 288         /*
 289          * After lpd init, powerkeys need to be written again to enable
 290          * low power detect function.
 291          */
 292         if (!rtc_powerkey_init()) {
 293                 ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
 294                 goto err;
 295         }
 296
 297         return RTC_STATUS_OK;
 298 err:
 299         rtc_info("init failed: ret = %d\n", ret);
 300         return ret;
 301 }
 302
 303 /* Enable RTC bbpu */
 304 void rtc_bbpu_power_on(void)
 305 {
 306         u16 bbpu;
 307         int ret;
 308
 309         /* Pull powerhold high, control by pmic */
 310         mt6366_set_power_hold(true);
 311
 312         /* Pull PWRBB high */
 313         bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_RELOAD | RTC_BBPU_PWREN;
 314         rtc_write(RTC_BBPU, bbpu);
 315         ret = rtc_write_trigger();
 316         rtc_info("rtc_write_trigger = %d\n", ret);
 317
 318         rtc_read(RTC_BBPU, &bbpu);
 319         rtc_info("done BBPU = %#x\n", bbpu);
 320 }
 321
 322 static void dcxo_init(void)
 323 {
 324         /* Buffer setting */
 325         rtc_write(PMIC_RG_DCXO_CW15, 0xA2AA);
 326         rtc_write(PMIC_RG_DCXO_CW13, 0x98E9);
 327         rtc_write(PMIC_RG_DCXO_CW16, 0x9855);
 328
 329         /* 26M enable control */
 330         /* Enable clock buffer XO_SOC, XO_CEL */
 331         rtc_write(PMIC_RG_DCXO_CW00, 0x4805);
 332         rtc_write(PMIC_RG_DCXO_CW11, 0x8000);
 333
 334         /* Load thermal coefficient */
 335         rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7);
 336         rtc_write(PMIC_RG_DCXO_CW21, 0x12A7);
 337         rtc_write(PMIC_RG_DCXO_ELR0, 0xD004);
 338         rtc_write(PMIC_RG_TOP_TMA_KEY, 0x0000);
 339
 340         /* Adjust OSC FPM setting */
 341         rtc_write(PMIC_RG_DCXO_CW07, 0x8FFE);
 342
 343         /* Re-calibrate OSC current */
 344         rtc_write(PMIC_RG_DCXO_CW09, 0x008F);
 345         udelay(100);
 346         rtc_write(PMIC_RG_DCXO_CW09, 0x408F);
 347         mdelay(5);
 348
 349         rtc_set_capid(MT8186_RTC_DXCO_CAPID);
 350
 351         mt6366_dcxo_disable_unused();
 352 }
 353
 354 /* Initialize rtc boot flow */
 355 void rtc_boot(void)
 356 {
 357         /* DCXO clock initialized settings */
 358         dcxo_init();
 359
 360         /* DCXO 32k initialized settings */
 361         pwrap_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0);
 362         pwrap_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0);
 363
 364         /* Use DCXO 32K clock */
 365         if (!rtc_enable_dcxo())
 366                 rtc_info("rtc_enable_dcxo() failed\n");
 367
 368         rtc_boot_common();
 369         rtc_bbpu_power_on();
 370 }