src/soc/mediatek/mt8186/spm.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * This file is created based on MT8186 Functional Specification
   5  * Chapter number: 3.5
   6  */
   7
   8 #include <soc/mcu_common.h>
   9 #include <soc/spm.h>
  10
  11 static const struct pwr_ctrl spm_init_ctrl = {
  12         /* For SPM, this flag is not auto-gen. */
  13         .pcm_flags = SPM_FLAG_DISABLE_VCORE_DVS |
  14                      SPM_FLAG_DISABLE_VCORE_DFS |
  15                      SPM_FLAG_RUN_COMMON_SCENARIO,
  16
  17         /* Auto-gen Start */
  18
  19         /* SPM_AP_STANDBY_CON */
  20         .reg_wfi_op = 0,
  21         .reg_wfi_type = 0,
  22         .reg_mp0_cputop_idle_mask = 0,
  23         .reg_mp1_cputop_idle_mask = 0,
  24         .reg_mcusys_idle_mask = 0,
  25         .reg_md_apsrc_1_sel = 0,
  26         .reg_md_apsrc_0_sel = 0,
  27         .reg_conn_apsrc_sel = 0,
  28
  29         /* SPM_SRC6_MASK */
  30         .reg_ccif_event_infra_req_mask_b = 0xFFFF,
  31         .reg_ccif_event_apsrc_req_mask_b = 0xFFFF,
  32
  33         /* SPM_SRC_REQ */
  34         .reg_spm_apsrc_req = 0,
  35         .reg_spm_f26m_req = 0,
  36         .reg_spm_infra_req = 0,
  37         .reg_spm_vrf18_req = 0,
  38         .reg_spm_ddren_req = 0,
  39         .reg_spm_dvfs_req = 0,
  40         .reg_spm_sw_mailbox_req = 0,
  41         .reg_spm_sspm_mailbox_req = 0,
  42         .reg_spm_adsp_mailbox_req = 0,
  43         .reg_spm_scp_mailbox_req = 0,
  44
  45         /* SPM_SRC_MASK */
  46         .reg_md_0_srcclkena_mask_b = 1,
  47         .reg_md_0_infra_req_mask_b = 1,
  48         .reg_md_0_apsrc_req_mask_b = 1,
  49         .reg_md_0_vrf18_req_mask_b = 1,
  50         .reg_md_0_ddren_req_mask_b = 1,
  51         .reg_md_1_srcclkena_mask_b = 0,
  52         .reg_md_1_infra_req_mask_b = 0,
  53         .reg_md_1_apsrc_req_mask_b = 0,
  54         .reg_md_1_vrf18_req_mask_b = 0,
  55         .reg_md_1_ddren_req_mask_b = 0,
  56         .reg_conn_srcclkena_mask_b = 1,
  57         .reg_conn_srcclkenb_mask_b = 0,
  58         .reg_conn_infra_req_mask_b = 1,
  59         .reg_conn_apsrc_req_mask_b = 1,
  60         .reg_conn_vrf18_req_mask_b = 1,
  61         .reg_conn_ddren_req_mask_b = 1,
  62         .reg_conn_vfe28_mask_b = 0,
  63         .reg_srcclkeni_srcclkena_mask_b = 1,
  64         .reg_srcclkeni_infra_req_mask_b = 1,
  65         .reg_infrasys_apsrc_req_mask_b = 0,
  66         .reg_infrasys_ddren_req_mask_b = 1,
  67         .reg_sspm_srcclkena_mask_b = 1,
  68         .reg_sspm_infra_req_mask_b = 1,
  69         .reg_sspm_apsrc_req_mask_b = 1,
  70         .reg_sspm_vrf18_req_mask_b = 1,
  71         .reg_sspm_ddren_req_mask_b = 1,
  72
  73         /* SPM_SRC2_MASK */
  74         .reg_scp_srcclkena_mask_b = 1,
  75         .reg_scp_infra_req_mask_b = 1,
  76         .reg_scp_apsrc_req_mask_b = 1,
  77         .reg_scp_vrf18_req_mask_b = 1,
  78         .reg_scp_ddren_req_mask_b = 1,
  79         .reg_audio_dsp_srcclkena_mask_b = 1,
  80         .reg_audio_dsp_infra_req_mask_b = 1,
  81         .reg_audio_dsp_apsrc_req_mask_b = 1,
  82         .reg_audio_dsp_vrf18_req_mask_b = 1,
  83         .reg_audio_dsp_ddren_req_mask_b = 1,
  84         .reg_ufs_srcclkena_mask_b = 1,
  85         .reg_ufs_infra_req_mask_b = 1,
  86         .reg_ufs_apsrc_req_mask_b = 1,
  87         .reg_ufs_vrf18_req_mask_b = 1,
  88         .reg_ufs_ddren_req_mask_b = 1,
  89         .reg_disp0_apsrc_req_mask_b = 1,
  90         .reg_disp0_ddren_req_mask_b = 1,
  91         .reg_disp1_apsrc_req_mask_b = 1,
  92         .reg_disp1_ddren_req_mask_b = 1,
  93         .reg_gce_infra_req_mask_b = 1,
  94         .reg_gce_apsrc_req_mask_b = 1,
  95         .reg_gce_vrf18_req_mask_b = 1,
  96         .reg_gce_ddren_req_mask_b = 1,
  97         .reg_apu_srcclkena_mask_b = 0,
  98         .reg_apu_infra_req_mask_b = 0,
  99         .reg_apu_apsrc_req_mask_b = 0,
 100         .reg_apu_vrf18_req_mask_b = 0,
 101         .reg_apu_ddren_req_mask_b = 0,
 102         .reg_cg_check_srcclkena_mask_b = 0,
 103         .reg_cg_check_apsrc_req_mask_b = 0,
 104         .reg_cg_check_vrf18_req_mask_b = 0,
 105         .reg_cg_check_ddren_req_mask_b = 0,
 106
 107         /* SPM_SRC3_MASK */
 108         .reg_dvfsrc_event_trigger_mask_b = 1,
 109         .reg_sw2spm_wakeup_mask_b = 0,
 110         .reg_adsp2spm_wakeup_mask_b = 0,
 111         .reg_sspm2spm_wakeup_mask_b = 0,
 112         .reg_scp2spm_wakeup_mask_b = 0,
 113         .reg_csyspwrup_ack_mask = 1,
 114         .reg_spm_reserved_srcclkena_mask_b = 0,
 115         .reg_spm_reserved_infra_req_mask_b = 0,
 116         .reg_spm_reserved_apsrc_req_mask_b = 0,
 117         .reg_spm_reserved_vrf18_req_mask_b = 0,
 118         .reg_spm_reserved_ddren_req_mask_b = 0,
 119         .reg_mcupm_srcclkena_mask_b = 1,
 120         .reg_mcupm_infra_req_mask_b = 1,
 121         .reg_mcupm_apsrc_req_mask_b = 1,
 122         .reg_mcupm_vrf18_req_mask_b = 1,
 123         .reg_mcupm_ddren_req_mask_b = 1,
 124         .reg_msdc0_srcclkena_mask_b = 1,
 125         .reg_msdc0_infra_req_mask_b = 1,
 126         .reg_msdc0_apsrc_req_mask_b = 1,
 127         .reg_msdc0_vrf18_req_mask_b = 1,
 128         .reg_msdc0_ddren_req_mask_b = 1,
 129         .reg_msdc1_srcclkena_mask_b = 1,
 130         .reg_msdc1_infra_req_mask_b = 1,
 131         .reg_msdc1_apsrc_req_mask_b = 1,
 132         .reg_msdc1_vrf18_req_mask_b = 1,
 133         .reg_msdc1_ddren_req_mask_b = 1,
 134
 135         /* SPM_SRC4_MASK */
 136         .reg_ccif_event_srcclkena_mask_b = 0x3FF,
 137         .reg_bak_psri_srcclkena_mask_b = 0,
 138         .reg_bak_psri_infra_req_mask_b = 0,
 139         .reg_bak_psri_apsrc_req_mask_b = 0,
 140         .reg_bak_psri_vrf18_req_mask_b = 0,
 141         .reg_bak_psri_ddren_req_mask_b = 0,
 142         .reg_dramc_md32_infra_req_mask_b = 1,
 143         .reg_dramc_md32_vrf18_req_mask_b = 0,
 144         .reg_conn_srcclkenb2pwrap_mask_b = 0,
 145         .reg_dramc_md32_apsrc_req_mask_b = 0,
 146
 147         /* SPM_SRC5_MASK */
 148         .reg_mcusys_merge_apsrc_req_mask_b = 0x14,
 149         .reg_mcusys_merge_ddren_req_mask_b = 0x14,
 150         .reg_afe_srcclkena_mask_b = 0,
 151         .reg_afe_infra_req_mask_b = 0,
 152         .reg_afe_apsrc_req_mask_b = 0,
 153         .reg_afe_vrf18_req_mask_b = 0,
 154         .reg_afe_ddren_req_mask_b = 0,
 155         .reg_msdc2_srcclkena_mask_b = 0,
 156         .reg_msdc2_infra_req_mask_b = 0,
 157         .reg_msdc2_apsrc_req_mask_b = 0,
 158         .reg_msdc2_vrf18_req_mask_b = 0,
 159         .reg_msdc2_ddren_req_mask_b = 0,
 160
 161         /* SPM_WAKEUP_EVENT_MASK */
 162         .reg_wakeup_event_mask = 0xEFFFFFFF,
 163
 164         /* SPM_WAKEUP_EVENT_EXT_MASK */
 165         .reg_ext_wakeup_event_mask = 0xFFFFFFFF,
 166
 167         /* SPM_SRC7_MASK */
 168         .reg_pcie_srcclkena_mask_b = 0,
 169         .reg_pcie_infra_req_mask_b = 0,
 170         .reg_pcie_apsrc_req_mask_b = 0,
 171         .reg_pcie_vrf18_req_mask_b = 0,
 172         .reg_pcie_ddren_req_mask_b = 0,
 173         .reg_dpmaif_srcclkena_mask_b = 1,
 174         .reg_dpmaif_infra_req_mask_b = 1,
 175         .reg_dpmaif_apsrc_req_mask_b = 1,
 176         .reg_dpmaif_vrf18_req_mask_b = 1,
 177         .reg_dpmaif_ddren_req_mask_b = 1,
 178
 179         /* Auto-gen End */
 180 };
 181
 182 void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
 183 {
 184         /* Auto-gen Start */
 185
 186         /* SPM_AP_STANDBY_CON */
 187         write32(&mtk_spm->spm_ap_standby_con,
 188                 ((pwrctrl->reg_wfi_op & 0x1) << 0) |
 189                 ((pwrctrl->reg_wfi_type & 0x1) << 1) |
 190                 ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
 191                 ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
 192                 ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
 193                 ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
 194                 ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
 195                 ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
 196
 197         /* SPM_SRC6_MASK */
 198         write32(&mtk_spm->spm_src6_mask,
 199                 ((pwrctrl->reg_ccif_event_infra_req_mask_b & 0xffff) << 0) |
 200                 ((pwrctrl->reg_ccif_event_apsrc_req_mask_b & 0xffff) << 16));
 201
 202         /* SPM_SRC_REQ */
 203         write32(&mtk_spm->spm_src_req,
 204                 ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
 205                 ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
 206                 ((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
 207                 ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
 208                 ((pwrctrl->reg_spm_ddren_req & 0x1) << 7) |
 209                 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
 210                 ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
 211                 ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
 212                 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
 213                 ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
 214
 215         /* SPM_SRC_MASK */
 216         write32(&mtk_spm->spm_src_mask,
 217                 ((pwrctrl->reg_md_0_srcclkena_mask_b & 0x1) << 0) |
 218                 ((pwrctrl->reg_md_0_infra_req_mask_b & 0x1) << 1) |
 219                 ((pwrctrl->reg_md_0_apsrc_req_mask_b & 0x1) << 2) |
 220                 ((pwrctrl->reg_md_0_vrf18_req_mask_b & 0x1) << 3) |
 221                 ((pwrctrl->reg_md_0_ddren_req_mask_b & 0x1) << 4) |
 222                 ((pwrctrl->reg_md_1_srcclkena_mask_b & 0x1) << 5) |
 223                 ((pwrctrl->reg_md_1_infra_req_mask_b & 0x1) << 6) |
 224                 ((pwrctrl->reg_md_1_apsrc_req_mask_b & 0x1) << 7) |
 225                 ((pwrctrl->reg_md_1_vrf18_req_mask_b & 0x1) << 8) |
 226                 ((pwrctrl->reg_md_1_ddren_req_mask_b & 0x1) << 9) |
 227                 ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 10) |
 228                 ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 11) |
 229                 ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 12) |
 230                 ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 13) |
 231                 ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 14) |
 232                 ((pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 15) |
 233                 ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 16) |
 234                 ((pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x7) << 17) |
 235                 ((pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x7) << 20) |
 236                 ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) |
 237                 ((pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 26) |
 238                 ((pwrctrl->reg_sspm_srcclkena_mask_b & 0x1) << 27) |
 239                 ((pwrctrl->reg_sspm_infra_req_mask_b & 0x1) << 28) |
 240                 ((pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 29) |
 241                 ((pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 30) |
 242                 ((pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 31));
 243
 244         /* SPM_SRC2_MASK */
 245         write32(&mtk_spm->spm_src2_mask,
 246                 ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) |
 247                 ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) |
 248                 ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) |
 249                 ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) |
 250                 ((pwrctrl->reg_scp_ddren_req_mask_b & 0x1) << 4) |
 251                 ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) |
 252                 ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) |
 253                 ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) |
 254                 ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) |
 255                 ((pwrctrl->reg_audio_dsp_ddren_req_mask_b & 0x1) << 9) |
 256                 ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) |
 257                 ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) |
 258                 ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) |
 259                 ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) |
 260                 ((pwrctrl->reg_ufs_ddren_req_mask_b & 0x1) << 14) |
 261                 ((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) |
 262                 ((pwrctrl->reg_disp0_ddren_req_mask_b & 0x1) << 16) |
 263                 ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) |
 264                 ((pwrctrl->reg_disp1_ddren_req_mask_b & 0x1) << 18) |
 265                 ((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) |
 266                 ((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) |
 267                 ((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) |
 268                 ((pwrctrl->reg_gce_ddren_req_mask_b & 0x1) << 22) |
 269                 ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) |
 270                 ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) |
 271                 ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) |
 272                 ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) |
 273                 ((pwrctrl->reg_apu_ddren_req_mask_b & 0x1) << 27) |
 274                 ((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) |
 275                 ((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) |
 276                 ((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) |
 277                 ((pwrctrl->reg_cg_check_ddren_req_mask_b & 0x1) << 31));
 278
 279         /* SPM_SRC3_MASK */
 280         write32(&mtk_spm->spm_src3_mask,
 281                 ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) |
 282                 ((pwrctrl->reg_sw2spm_wakeup_mask_b & 0xf) << 1) |
 283                 ((pwrctrl->reg_adsp2spm_wakeup_mask_b & 0x1) << 5) |
 284                 ((pwrctrl->reg_sspm2spm_wakeup_mask_b & 0xf) << 6) |
 285                 ((pwrctrl->reg_scp2spm_wakeup_mask_b & 0x1) << 10) |
 286                 ((pwrctrl->reg_csyspwrup_ack_mask & 0x1) << 11) |
 287                 ((pwrctrl->reg_spm_reserved_srcclkena_mask_b & 0x1) << 12) |
 288                 ((pwrctrl->reg_spm_reserved_infra_req_mask_b & 0x1) << 13) |
 289                 ((pwrctrl->reg_spm_reserved_apsrc_req_mask_b & 0x1) << 14) |
 290                 ((pwrctrl->reg_spm_reserved_vrf18_req_mask_b & 0x1) << 15) |
 291                 ((pwrctrl->reg_spm_reserved_ddren_req_mask_b & 0x1) << 16) |
 292                 ((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) |
 293                 ((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) |
 294                 ((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) |
 295                 ((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) |
 296                 ((pwrctrl->reg_mcupm_ddren_req_mask_b & 0x1) << 21) |
 297                 ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) |
 298                 ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) |
 299                 ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) |
 300                 ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) |
 301                 ((pwrctrl->reg_msdc0_ddren_req_mask_b & 0x1) << 26) |
 302                 ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) |
 303                 ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) |
 304                 ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) |
 305                 ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) |
 306                 ((pwrctrl->reg_msdc1_ddren_req_mask_b & 0x1) << 31));
 307
 308         /* SPM_SRC4_MASK */
 309         write32(&mtk_spm->spm_src4_mask,
 310                 ((pwrctrl->reg_ccif_event_srcclkena_mask_b & 0xffff) << 0) |
 311                 ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) |
 312                 ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) |
 313                 ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) |
 314                 ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) |
 315                 ((pwrctrl->reg_bak_psri_ddren_req_mask_b & 0x1) << 20) |
 316                 ((pwrctrl->reg_dramc_md32_infra_req_mask_b & 0x3) << 21) |
 317                 ((pwrctrl->reg_dramc_md32_vrf18_req_mask_b & 0x3) << 23) |
 318                 ((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) |
 319                 ((pwrctrl->reg_dramc_md32_apsrc_req_mask_b & 0x3) << 26));
 320
 321         /* SPM_SRC5_MASK */
 322         write32(&mtk_spm->spm_src5_mask,
 323                 ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) |
 324                 ((pwrctrl->reg_mcusys_merge_ddren_req_mask_b & 0x1ff) << 9) |
 325                 ((pwrctrl->reg_afe_srcclkena_mask_b & 0x1) << 18) |
 326                 ((pwrctrl->reg_afe_infra_req_mask_b & 0x1) << 19) |
 327                 ((pwrctrl->reg_afe_apsrc_req_mask_b & 0x1) << 20) |
 328                 ((pwrctrl->reg_afe_vrf18_req_mask_b & 0x1) << 21) |
 329                 ((pwrctrl->reg_afe_ddren_req_mask_b & 0x1) << 22) |
 330                 ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 23) |
 331                 ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 24) |
 332                 ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 25) |
 333                 ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 26) |
 334                 ((pwrctrl->reg_msdc2_ddren_req_mask_b & 0x1) << 27));
 335
 336         /* SPM_WAKEUP_EVENT_MASK */
 337         write32(&mtk_spm->spm_wakeup_event_mask,
 338                 ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
 339
 340         /* SPM_WAKEUP_EVENT_EXT_MASK */
 341         write32(&mtk_spm->spm_wakeup_event_ext_mask,
 342                 ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
 343
 344         /* SPM_SRC7_MASK */
 345         write32(&mtk_spm->spm_src7_mask,
 346                 ((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 0) |
 347                 ((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 1) |
 348                 ((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 2) |
 349                 ((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 3) |
 350                 ((pwrctrl->reg_pcie_ddren_req_mask_b & 0x1) << 4) |
 351                 ((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 5) |
 352                 ((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 6) |
 353                 ((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 7) |
 354                 ((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 8) |
 355                 ((pwrctrl->reg_dpmaif_ddren_req_mask_b & 0x1) << 9));
 356         /* Auto-gen End */
 357
 358         /* Disable unused optional components */
 359         write32(&mtk_spm->nna_pwr_con, BIT(1) | BIT(4) | BIT(8));
 360 }
 361
 362 static void spm_hw_s1_state_monitor(int en)
 363 {
 364         if (en)
 365                 SET32_BITFIELDS(&mtk_spm->spm_ack_chk_con_3,
 366                                 SPM_ACK_CHK_3_CON_CLR_ALL, 0,
 367                                 SPM_ACK_CHK_3_CON_EN_0, 1,
 368                                 SPM_ACK_CHK_3_CON_EN_1, 1);
 369         else
 370                 SET32_BITFIELDS(&mtk_spm->spm_ack_chk_con_3,
 371                                 SPM_ACK_CHK_3_CON_HW_MODE_TRIG_0, 1,
 372                                 SPM_ACK_CHK_3_CON_HW_MODE_TRIG_1, 1,
 373                                 SPM_ACK_CHK_3_CON_CLR_ALL, 1,
 374                                 SPM_ACK_CHK_3_CON_EN_0, 0,
 375                                 SPM_ACK_CHK_3_CON_EN_1, 0);
 376 }
 377
 378 void spm_register_init(void)
 379 {
 380         /* Enable register control */
 381         write32(&mtk_spm->poweron_config_set,
 382                 SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
 383
 384         /* Init power control register */
 385         write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF);
 386         write32(&mtk_spm->pcm_pwr_io_en, 0);
 387
 388         /* Reset PCM */
 389         write32(&mtk_spm->pcm_con0,
 390                 SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB);
 391         write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
 392         write32(&mtk_spm->pcm_con1,
 393                 SPM_REGWR_CFG_KEY | RG_AHBMIF_APBEN_LSB |
 394                 REG_MD32_APB_INTERNAL_EN_LSB);
 395
 396         /* Initial SPM CLK control register */
 397         SET32_BITFIELDS(&mtk_spm->spm_clk_con,
 398                         REG_SYSCLK1_SRC_MD2_SRCCLKENA, 1);
 399
 400         /* Clean wakeup event raw status */
 401         write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF);
 402
 403         /* Clean ISR status */
 404         write32(&mtk_spm->spm_irq_mask, ISRM_ALL);
 405         write32(&mtk_spm->spm_irq_sta, ISRC_ALL);
 406         write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL);
 407
 408         /* Init r7 with POWER_ON_VAL1 */
 409         write32(&mtk_spm->pcm_reg_data_ini,
 410                 read32(&mtk_spm->spm_power_on_val1));
 411         write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
 412         write32(&mtk_spm->pcm_pwr_io_en, 0);
 413
 414         /* DDR EN de-bounce length to 5us */
 415         write32(&mtk_spm->ddren_dbc_con, DDREN_DBC_EN_VAL | REG_DDREN_DBC_EN_LSB);
 416
 417         /* Configure ARMPLL Control Mode for MCDI */
 418         write32(&mtk_spm->armpll_clk_sel, ARMPLL_CLK_SEL_DEF);
 419
 420         /* Init for SPM Resource ACK */
 421         write32(&mtk_spm->spm_resource_ack_con0, SPM_RESOURCE_ACK_CON0_DEF);
 422         write32(&mtk_spm->spm_resource_ack_con1, SPM_RESOURCE_ACK_CON1_DEF);
 423         write32(&mtk_spm->spm_resource_ack_con2, SPM_RESOURCE_ACK_CON2_DEF);
 424         write32(&mtk_spm->spm_resource_ack_con3, SPM_RESOURCE_ACK_CON3_DEF);
 425
 426         /* Enable Side-Band */
 427         write32((void *)AP_PLL_CON3, APMIX_CON3_DEF);
 428         write32((void *)AP_PLL_CON4, APMIX_CON4_DEF);
 429         write32((void *)CLK_SCP_CFG_0, SCP_CFG0_DEF);
 430         write32((void *)CLK_SCP_CFG_1, SCP_CFG1_DEF);
 431
 432         /* Init VCORE DVFS Status */
 433         SET32_BITFIELDS(&mtk_spm->spm_dvfs_misc,
 434                         SPM_DVFS_FORCE_ENABLE_LSB, 0,
 435                         SPM_DVFSRC_ENABLE_LSB, 1);
 436         write32(&mtk_spm->spm_dvfs_level, SPM_DVFS_LEVEL_DEF);
 437         write32(&mtk_spm->spm_dvs_dfs_level, SPM_DVS_DFS_LEVEL_DEF);
 438
 439         write32(&mtk_spm->spm_ack_chk_sel_3, SPM_ACK_CHK_3_SEL_HW_S1);
 440         write32(&mtk_spm->spm_ack_chk_timer_3, SPM_ACK_CHK_3_HW_S1_CNT);
 441
 442         spm_hw_s1_state_monitor(0);
 443 }
 444
 445 void spm_extern_initialize(void)
 446 {
 447         SET32_BITFIELDS(&mtk_spm->spm_dvfs_misc,
 448                         INFRA_AO_RES_CTRL_MASK_EMI_IDLE, 1,
 449                         INFRA_AO_RES_CTRL_MASK_MPU_IDLE, 1);
 450 }
 451
 452 void spm_reset_and_init_pcm(void)
 453 {
 454         bool first_load_fw = true;
 455
 456         /* Check whether the SPM FW is running */
 457         if (read32(&mtk_spm->md32pcm_cfgreg_sw_rstn) & MD32PCM_CFGREG_SW_RSTN_RUN)
 458                 first_load_fw = false;
 459
 460         if (!first_load_fw) {
 461                 spm_code_swapping();
 462                 /* Backup PCM r0 -> SPM_POWER_ON_VAL0 before reset PCM */
 463                 write32(&mtk_spm->spm_power_on_val0,
 464                         read32(&mtk_spm->pcm_reg0_data));
 465         }
 466
 467         /* Disable r0 and r7 to control power */
 468         write32(&mtk_spm->pcm_pwr_io_en, 0);
 469
 470         /* Disable pcm timer after leaving FW */
 471         clrsetbits32(&mtk_spm->pcm_con1,
 472                      RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
 473
 474         /* Reset PCM */
 475         write32(&mtk_spm->pcm_con0,
 476                 SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB);
 477         write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
 478
 479         /* Init PCM_CON1 (disable PCM timer but keep PCM WDT setting) */
 480         clrsetbits32(&mtk_spm->pcm_con1, ~RG_PCM_WDT_WAKE_LSB,
 481                      SPM_REGWR_CFG_KEY | RG_AHBMIF_APBEN_LSB | REG_MD32_APB_INTERNAL_EN_LSB);
 482 }
 483
 484 void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
 485 {
 486         u32 val, mask;
 487
 488         /* Toggle event counter clear */
 489         setbits32(&mtk_spm->pcm_con1,
 490                   SPM_REGWR_CFG_KEY | REG_SPM_EVENT_COUNTER_CLR_LSB);
 491
 492         /* Toggle for reset SYS TIMER start point */
 493         SET32_BITFIELDS(&mtk_spm->sys_timer_con,
 494                         SYS_TIMER_START_EN_LSB, 1);
 495
 496         if (pwrctrl->timer_val_cust == 0)
 497                 val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX;
 498         else
 499                 val = pwrctrl->timer_val_cust;
 500
 501         write32(&mtk_spm->pcm_timer_val, val);
 502
 503         setbits32(&mtk_spm->pcm_con1, RG_PCM_TIMER_EN_LSB | SPM_REGWR_CFG_KEY);
 504
 505         /* Unmask AP wakeup source */
 506         if (pwrctrl->wake_src_cust == 0)
 507                 mask = pwrctrl->wake_src;
 508         else
 509                 mask = pwrctrl->wake_src_cust;
 510
 511         if (pwrctrl->reg_csyspwrup_ack_mask)
 512                 mask &= ~R12_CSYSPWREQ_B;
 513         write32(&mtk_spm->spm_wakeup_event_mask, ~mask);
 514
 515         /* Unmask SPM ISR */
 516         setbits32(&mtk_spm->spm_irq_mask, ISRM_RET_IRQ_AUX);
 517
 518         /* Toggle event counter clear */
 519         clrsetbits32(&mtk_spm->pcm_con1, REG_SPM_EVENT_COUNTER_CLR_LSB, SPM_REGWR_CFG_KEY);
 520
 521         /* Toggle for reset SYS TIMER start point */
 522         SET32_BITFIELDS(&mtk_spm->sys_timer_con,
 523                         SYS_TIMER_START_EN_LSB, 0);
 524 }
 525
 526 const struct pwr_ctrl *get_pwr_ctrl(void)
 527 {
 528         return &spm_init_ctrl;
 529 }