src/soc/mediatek/mt8196/mminfra.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/mmio.h>
   5 #include <soc/addressmap.h>
   6 #include <soc/mminfra.h>
   7 #include <soc/spm_mtcmos.h>
   8 #include <stddef.h>
   9 #include <string.h>
  10 #include <timer.h>
  11 #include <types.h>
  12
  13 #define TIMEOUT_US 20
  14
  15 static void wait_for_write_done(u32 write_reg, u32 status_reg, u32 val)
  16 {
  17         write32p(write_reg, val);
  18
  19         if (!wait_us(TIMEOUT_US, read32p(status_reg) == val))
  20                 die("Wait write done timeout\n");
  21 }
  22
  23 static void mm_gce_lock_prot_en(void)
  24 {
  25         setbits32p(MMINFRA_GCE_PROT_EN,
  26                    GCE_D_SLEEPPORT_RX_EN | GCE_D_HAND_SLEEPPORT_RX_EN |
  27                    GCE_D_HAND_SLEEPPORT_TX_EN | GCE_M_SLEEPPORT_RX_EN |
  28                    GCE_M_HAND_SLEEPPORT_RX_EN | GCE_M_HAND_SLEEPPORT_TX_EN);
  29 }
  30
  31 static void mm_gce_release_prot_en(void)
  32 {
  33         write32p(MMINFRA_GCE_PROT_EN, 0);
  34 }
  35
  36 static void mm_infra0_lock_prot_en(void)
  37 {
  38         wait_for_write_done(MMINFRA_MM0_GALS_PROT_TX_EN,
  39                             MMINFRA_MM0_GALS_PROT_TX_RDY, 0xff);
  40         wait_for_write_done(MMINFRA_MM0_GALS_PROT_RX_EN,
  41                             MMINFRA_MM0_GALS_PROT_RX_RDY, 0xfffff);
  42 }
  43
  44 static void mm_infra0_release_prot_en(void)
  45 {
  46         write32p(MMINFRA_MM0_GALS_PROT_RX_EN, 0);
  47         write32p(MMINFRA_MM0_GALS_PROT_TX_EN, 0);
  48 }
  49
  50 static void mm_infra1_lock_prot_en(void)
  51 {
  52         mm_gce_lock_prot_en();
  53         wait_for_write_done(MMINFRA_MM1_GALS_PROT_TX_EN,
  54                             MMINFRA_MM1_GALS_PROT_TX_RDY, 0x3f);
  55         wait_for_write_done(MMINFRA_MM1_GALS_PROT_RX_EN,
  56                             MMINFRA_MM1_GALS_PROT_RX_RDY, 0xf);
  57 }
  58
  59 static void mm_infra1_release_prot_en(void)
  60 {
  61         write32p(MMINFRA_MM1_GALS_PROT_RX_EN, 0);
  62         write32p(MMINFRA_MM1_GALS_PROT_TX_EN, 0);
  63         mm_gce_release_prot_en();
  64 }
  65
  66 static int pd_mm_infra0_pre_on(void)
  67 {
  68         setbits32p(MMPC_PM_BOOT_UP_PWR_CON, MM_INFRA0_PM_BOOT_UP | MM_INFRA1_PM_BOOT_UP);
  69         return 0;
  70 }
  71
  72 static int pd_mm_infra0_post_on(void)
  73 {
  74         mm_infra0_release_prot_en();
  75         return 0;
  76 }
  77
  78 static int pd_mm_infra0_pre_off(void)
  79 {
  80         mm_infra0_lock_prot_en();
  81         return 0;
  82 }
  83
  84 static int pd_mm_infra1_post_on(void)
  85 {
  86         mm_infra1_release_prot_en();
  87         write32p(VLP_AO_RSVD6, 0x1);
  88         return 0;
  89 }
  90
  91 static int pd_mm_infra1_pre_off(void)
  92 {
  93         mm_infra1_lock_prot_en();
  94         return 0;
  95 }
  96
  97 static struct mtcmos_cb mm_infra0_pb_cb = {
  98         .pre_on = pd_mm_infra0_pre_on,
  99         .post_on = pd_mm_infra0_post_on,
 100         .pre_off = pd_mm_infra0_pre_off,
 101 };
 102
 103 static struct mtcmos_cb mm_infra1_pb_cb = {
 104         .post_on = pd_mm_infra1_post_on,
 105         .pre_off = pd_mm_infra1_pre_off,
 106 };
 107
 108 void mminfra_post_init(void)
 109 {
 110         if (mtcmos_cb_register(MTCMOS_ID_MM_INFRA0, &mm_infra0_pb_cb))
 111                 return;
 112
 113         mtcmos_cb_register(MTCMOS_ID_MM_INFRA1, &mm_infra1_pb_cb);
 114 }