src/soc/mediatek/mt8196/mtcmos.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * This file is created based on MTCMOS_SW_NOTE.xlsx
   5  */
   6
   7 #include <console/console.h>
   8 #include <delay.h>
   9 #include <soc/addressmap.h>
  10 #include <soc/mtcmos.h>
  11 #include <soc/pll.h>
  12 #include <soc/spm_mtcmos.h>
  13 #include <timer.h>
  14
  15 #define MTK_SCPD_CAPS(_scpd, _x)        ((_scpd)->caps & (_x))
  16
  17 #define POWERON_CONFIG_EN       ((void *)(SPM_BASE + 0x0000))
  18
  19 #define SPM_PROJECT_CODE        0xB16
  20
  21 #define SET_BUS_PROTECT         1
  22 #define RELEASE_BUS_PROTECT     0
  23
  24 #define WAIT_VOTE_TIMEOUT       20000
  25
  26 #define SPM_PBUS_BUS_PROTECT_EN_SET             ((void *)(SPM_PBUS_BASE + 0x00DC))
  27 #define SPM_PBUS_BUS_PROTECT_EN_CLR             ((void *)(SPM_PBUS_BASE + 0x00E0))
  28 #define SPM_PBUS_BUS_PROTECT_RDY_STA            ((void *)(SPM_PBUS_BASE + 0x0208))
  29 #define SPM_PBUS_BUS_MSB_PROTECT_EN_SET         ((void *)(SPM_PBUS_BASE + 0x00E8))
  30 #define SPM_PBUS_BUS_MSB_PROTECT_EN_CLR         ((void *)(SPM_PBUS_BASE + 0x00EC))
  31 #define SPM_PBUS_BUS_MSB_PROTECT_RDY_STA        ((void *)(SPM_PBUS_BASE + 0x020C))
  32
  33 #define MM_BUCK_ISO_CON_CLR             ((void *)(MMPC_BASE + 0x00C8))
  34 #define DISP_AO_PWR_CON                 ((void *)(MMPC_BASE + 0x00E8))
  35 #define MMPC_BUS_PROTECT_EN_1_CLR       ((void *)(MMPC_BASE + 0x0188))
  36
  37 #define MMVOTE_MTCMOS_0_SET             ((void *)(MMVOTE_BASE + 0x0218))
  38 #define MMVOTE_MTCMOS_0_CLR             ((void *)(MMVOTE_BASE + 0x021C))
  39 #define MMVOTE_MTCMOS_0_DONE            ((void *)(MMVOTE_BASE + 0x141C))
  40 #define MMVOTE_MTCMOS_0_PM_ACK          ((void *)(MMVOTE_BASE + 0x5514))
  41 #define MMVOTE_MTCMOS_1_SET             ((void *)(MMVOTE_BASE + 0x0220))
  42 #define MMVOTE_MTCMOS_1_CLR             ((void *)(MMVOTE_BASE + 0x0224))
  43 #define MMVOTE_MTCMOS_1_DONE            ((void *)(MMVOTE_BASE + 0x142C))
  44 #define MMVOTE_MTCMOS_1_PM_ACK          ((void *)(MMVOTE_BASE + 0x5518))
  45 #define MMINFRA_MTCMOS_1_SET            ((void *)(MMVOTE_BASE + 0x43220))
  46 #define MMINFRA_MTCMOS_1_CLR            ((void *)(MMVOTE_BASE + 0x43224))
  47
  48 #define DISP_VDISP_AO_CONFIG_CG         0x3E800108
  49 #define DISP_DPC_DISP0_MTCMOS_CFG       0x3E8F0500
  50 #define DISP_DPC_DISP1_MTCMOS_CFG       0x3E8F0580
  51 #define DISP_DPC_OVL0_MTCMOS_CFG        0x3E8F0600
  52 #define DISP_DPC_OVL1_MTCMOS_CFG        0x3E8F0680
  53 #define DISP_DPC_MML0_MTCMOS_CFG        0x3E8F0B00
  54 #define DISP_DPC_MML1_MTCMOS_CFG        0x3E8F0700
  55 #define DISP_DPC_EDP_MTCMOS_CFG         0x3E8F0C00
  56 #define DISP_DPC_EPTX_MTCMOS_CFG        0x3E8F0D00
  57
  58 #define MMINFRA0_VOTE_BIT       1
  59 #define MMINFRA1_VOTE_BIT       2
  60 #define MMINFRA_AO_VOTE_BIT     3
  61 #define DSI_PHY0_VOTE_BIT       7
  62 #define DSI_PHY1_VOTE_BIT       8
  63 #define DSI_PHY2_VOTE_BIT       9
  64 #define DISP_VCORE_VOTE_BIT     24
  65 #define DISP0_VOTE_BIT          25
  66 #define DISP1_VOTE_BIT          26
  67 #define OVL0_VOTE_BIT           27
  68 #define OVL1_VOTE_BIT           28
  69 #define DISP_EDPTX_VOTE_BIT     29
  70 #define DISP_DPTX_VOTE_BIT      30
  71
  72 #define MTK_SCPD_SRAM_ISO       BIT(0)
  73 #define MTK_SCPD_SRAM_SLP       BIT(2)
  74 #define MTK_SCPD_RTFF_DELAY     BIT(6)
  75 #define MTK_SCPD_NO_SRAM        BIT(8)
  76
  77 #define PWR_RST_B               BIT(0)
  78 #define PWR_ISO                 BIT(1)
  79 #define PWR_ON                  BIT(2)
  80 #define PWR_ON_2ND              BIT(3)
  81 #define PWR_CLK_DIS             BIT(4)
  82 #define SRAM_CKISO              BIT(5)
  83 #define SRAM_ISOINT_B           BIT(6)
  84 #define SRAM_PDN                BIT(8)
  85 #define SRAM_SLP                BIT(9)
  86 #define SRAM_PDN_ACK            BIT(12)
  87 #define SRAM_SLP_ACK            BIT(13)
  88 #define PWR_RTFF_SAVE           BIT(24)
  89 #define PWR_RTFF_SAVE_FLAG      BIT(27)
  90 #define PWR_ACK                 BIT(30)
  91 #define PWR_ACK_2ND             BIT(31)
  92
  93 #define ACK_DELAY_US            10
  94 #define ACK_DELAY_TIMES         10000
  95
  96 #define ADSP_AO_PROT_STEP1_SHIFT                23
  97 #define ADSP_INFRA_PROT_STEP1_SHIFT             22
  98 #define ADSP_TOP_PROT_STEP1_SHIFT               21
  99 #define AUDIO_PROT_STEP1_SHIFT                  19
 100 #define MM_PROC_PROT_STEP1_SHIFT                24
 101 #define PEXTP_MAC0_PROT_STEP1_SHIFT             13
 102 #define PEXTP_MAC1_PROT_STEP1_SHIFT             14
 103 #define PEXTP_MAC2_PROT_STEP1_SHIFT             15
 104 #define PEXTP_PHY0_PROT_STEP1_SHIFT             16
 105 #define PEXTP_PHY1_PROT_STEP1_SHIFT             17
 106 #define PEXTP_PHY2_PROT_STEP1_SHIFT             18
 107 #define SSRSYS_PROT_STEP1_SHIFT                 10
 108 #define SSUSB_DP_PHY_P0_PROT_STEP1_SHIFT        6
 109 #define SSUSB_P0_PROT_STEP1_SHIFT               7
 110 #define SSUSB_P1_PROT_STEP1_SHIFT               8
 111 #define SSUSB_P23_PROT_STEP1_SHIFT              9
 112 #define SSUSB_PHY_P2_PROT_STEP1_SHIFT           10
 113 #define UFS0_PHY_PROT_STEP1_SHIFT               12
 114 #define UFS0_PROT_STEP1_SHIFT                   11
 115
 116 struct mtcmos_bus_prot {
 117         u32 *bp_en_set;
 118         u32 *bp_en_clr;
 119         u32 *bp_rdy;
 120         u8 bit;
 121 };
 122
 123 struct mtcmos_data {
 124         const struct mtcmos_bus_prot *bp_table;
 125         u32 *ctl_addr;
 126         u32 caps;
 127         u32 bp_num;
 128         const struct mtcmos_cb *cb;
 129 };
 130
 131 struct mtcmos_vote_data {
 132         u32 *set_addr;
 133         u32 *clr_addr;
 134         u32 *done_addr;
 135         u32 *ack_addr;
 136         u8 vote_bit;
 137         const struct mtcmos_cb *cb;
 138 };
 139
 140 static const struct mtcmos_bus_prot ssusb_dp_phy_p0_bp[] = {
 141         { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR,
 142           SPM_PBUS_BUS_PROTECT_RDY_STA, SSUSB_DP_PHY_P0_PROT_STEP1_SHIFT },
 143 };
 144
 145 static const struct mtcmos_bus_prot ssusb_p0_bp[] = {
 146         { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR,
 147           SPM_PBUS_BUS_PROTECT_RDY_STA, SSUSB_P0_PROT_STEP1_SHIFT },
 148 };
 149
 150 static const struct mtcmos_bus_prot ssusb_p1_bp[] = {
 151         { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR,
 152           SPM_PBUS_BUS_PROTECT_RDY_STA, SSUSB_P1_PROT_STEP1_SHIFT },
 153 };
 154
 155 static const struct mtcmos_bus_prot ssusb_p23_bp[] = {
 156         { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR,
 157           SPM_PBUS_BUS_PROTECT_RDY_STA, SSUSB_P23_PROT_STEP1_SHIFT },
 158 };
 159
 160 static const struct mtcmos_bus_prot ssusb_phy_p2_bp[] = {
 161         { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR,
 162           SPM_PBUS_BUS_PROTECT_RDY_STA, SSUSB_PHY_P2_PROT_STEP1_SHIFT },
 163 };
 164
 165 static const struct mtcmos_bus_prot ufs0_bp[] = {
 166         { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR,
 167           SPM_PBUS_BUS_PROTECT_RDY_STA, UFS0_PROT_STEP1_SHIFT },
 168 };
 169
 170 static const struct mtcmos_bus_prot ufs0_phy_bp[] = {
 171         { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR,
 172           SPM_PBUS_BUS_PROTECT_RDY_STA, UFS0_PHY_PROT_STEP1_SHIFT },
 173 };
 174
 175 static const struct mtcmos_bus_prot pextp_mac0_bp[] = {
 176         { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR,
 177           SPM_PBUS_BUS_PROTECT_RDY_STA, PEXTP_MAC0_PROT_STEP1_SHIFT },
 178 };
 179
 180 static const struct mtcmos_bus_prot pextp_mac1_bp[] = {
 181         { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR,
 182           SPM_PBUS_BUS_PROTECT_RDY_STA, PEXTP_MAC1_PROT_STEP1_SHIFT },
 183 };
 184
 185 static const struct mtcmos_bus_prot pextp_mac2_bp[] = {
 186         { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR,
 187           SPM_PBUS_BUS_PROTECT_RDY_STA, PEXTP_MAC2_PROT_STEP1_SHIFT },
 188 };
 189
 190 static const struct mtcmos_bus_prot pextp_phy0_bp[] = {
 191         { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR,
 192           SPM_PBUS_BUS_PROTECT_RDY_STA, PEXTP_PHY0_PROT_STEP1_SHIFT },
 193 };
 194
 195 static const struct mtcmos_bus_prot pextp_phy1_bp[] = {
 196         { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR,
 197           SPM_PBUS_BUS_PROTECT_RDY_STA, PEXTP_PHY1_PROT_STEP1_SHIFT },
 198 };
 199
 200 static const struct mtcmos_bus_prot pextp_phy2_bp[] = {
 201         { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR,
 202           SPM_PBUS_BUS_PROTECT_RDY_STA, PEXTP_PHY2_PROT_STEP1_SHIFT },
 203 };
 204
 205 static const struct mtcmos_bus_prot audio_bp[] = {
 206         { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR,
 207           SPM_PBUS_BUS_PROTECT_RDY_STA, AUDIO_PROT_STEP1_SHIFT },
 208 };
 209
 210 static const struct mtcmos_bus_prot adsp_top_bp[] = {
 211         { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR,
 212           SPM_PBUS_BUS_PROTECT_RDY_STA, ADSP_TOP_PROT_STEP1_SHIFT },
 213 };
 214
 215 static const struct mtcmos_bus_prot adsp_infra_bp[] = {
 216         { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR,
 217           SPM_PBUS_BUS_PROTECT_RDY_STA, ADSP_INFRA_PROT_STEP1_SHIFT },
 218 };
 219
 220 static const struct mtcmos_bus_prot adsp_ao_bp[] = {
 221         { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR,
 222           SPM_PBUS_BUS_PROTECT_RDY_STA, ADSP_AO_PROT_STEP1_SHIFT },
 223 };
 224
 225 static const struct mtcmos_bus_prot mm_proc_bp[] = {
 226         { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR,
 227           SPM_PBUS_BUS_PROTECT_RDY_STA, MM_PROC_PROT_STEP1_SHIFT },
 228 };
 229
 230 static const struct mtcmos_bus_prot ssrsys_bp[] = {
 231         { SPM_PBUS_BUS_MSB_PROTECT_EN_SET, SPM_PBUS_BUS_MSB_PROTECT_EN_CLR,
 232           SPM_PBUS_BUS_MSB_PROTECT_RDY_STA, SSRSYS_PROT_STEP1_SHIFT },
 233 };
 234
 235 static struct mtcmos_data mds[MTCMOS_ID_NUM] = {
 236         [MTCMOS_ID_SSUSB_DP_PHY_P0] = {
 237                 ssusb_dp_phy_p0_bp, &mtk_spm_mtcmos->ssusb_dp_phy_p0_pwr_con,
 238                 MTK_SCPD_NO_SRAM, 1
 239         },
 240         [MTCMOS_ID_SSUSB_P0] = {
 241                 ssusb_p0_bp, &mtk_spm_mtcmos->ssusb_p0_pwr_con, 0, 1
 242         },
 243         [MTCMOS_ID_SSUSB_P1] = {
 244                 ssusb_p1_bp, &mtk_spm_mtcmos->ssusb_p1_pwr_con, 0, 1
 245         },
 246         [MTCMOS_ID_SSUSB_P23] = {
 247                 ssusb_p23_bp, &mtk_spm_mtcmos->ssusb_p23_pwr_con, MTK_SCPD_NO_SRAM, 1
 248         },
 249         [MTCMOS_ID_SSUSB_PHY_P2] = {
 250                 ssusb_phy_p2_bp, &mtk_spm_mtcmos->ssusb_phy_p2_pwr_con, 0, 1
 251         },
 252         [MTCMOS_ID_UFS0_SHUTDOWN] = {
 253                 ufs0_bp, &mtk_spm_mtcmos->ufs0_pwr_con, 0, 1
 254         },
 255         [MTCMOS_ID_UFS0_PHY] = {
 256                 ufs0_phy_bp, &mtk_spm_mtcmos->ufs0_phy_pwr_con, MTK_SCPD_NO_SRAM, 1
 257         },
 258         [MTCMOS_ID_PEXTP_MAC0] = {
 259                 pextp_mac0_bp, &mtk_spm_mtcmos->pextp_mac0_pwr_con, 0, 1
 260         },
 261         [MTCMOS_ID_PEXTP_MAC1] = {
 262                 pextp_mac1_bp, &mtk_spm_mtcmos->pextp_mac1_pwr_con, 0, 1
 263         },
 264         [MTCMOS_ID_PEXTP_MAC2] = {
 265                 pextp_mac2_bp, &mtk_spm_mtcmos->pextp_mac2_pwr_con, 0, 1
 266         },
 267         [MTCMOS_ID_PEXTP_PHY0] = {
 268                 pextp_phy0_bp, &mtk_spm_mtcmos->pextp_phy0_pwr_con, MTK_SCPD_NO_SRAM, 1
 269         },
 270         [MTCMOS_ID_PEXTP_PHY1] = {
 271                 pextp_phy1_bp, &mtk_spm_mtcmos->pextp_phy1_pwr_con, MTK_SCPD_NO_SRAM, 1
 272         },
 273         [MTCMOS_ID_PEXTP_PHY2] = {
 274                 pextp_phy2_bp, &mtk_spm_mtcmos->pextp_phy2_pwr_con, MTK_SCPD_NO_SRAM, 1
 275         },
 276         [MTCMOS_ID_AUDIO] = {
 277                 audio_bp, &mtk_spm_mtcmos->audio_pwr_con, 0, 1
 278         },
 279         [MTCMOS_ID_ADSP_TOP_SHUTDOWN] = {
 280                 adsp_top_bp, &mtk_spm_mtcmos->adsp_top_pwr_con, 0, 1
 281         },
 282         [MTCMOS_ID_ADSP_INFRA] = {
 283                 adsp_infra_bp, &mtk_spm_mtcmos->adsp_infra_pwr_con, MTK_SCPD_NO_SRAM, 1
 284         },
 285         [MTCMOS_ID_ADSP_AO] = {
 286                 adsp_ao_bp, &mtk_spm_mtcmos->adsp_ao_pwr_con, MTK_SCPD_NO_SRAM, 1
 287         },
 288         [MTCMOS_ID_MM_PROC_SHUTDOWN] = {
 289                 mm_proc_bp, &mtk_spm_mtcmos->mm_proc_pwr_con, 0, 1
 290         },
 291         [MTCMOS_ID_SSRSYS] = {
 292                 ssrsys_bp, &mtk_spm_mtcmos->ssrsys_pwr_con, 0, 1
 293         },
 294 };
 295
 296 static struct mtcmos_vote_data vote_mds[MTCMOS_ID_NUM] = {
 297         [MTCMOS_ID_DISP_VCORE] = {
 298                 MMVOTE_MTCMOS_0_SET, MMVOTE_MTCMOS_0_CLR, MMVOTE_MTCMOS_0_DONE,
 299                 MMVOTE_MTCMOS_0_PM_ACK, DISP_VCORE_VOTE_BIT
 300         },
 301         [MTCMOS_ID_DIS0_SHUTDOWN] = {
 302                 MMVOTE_MTCMOS_0_SET, MMVOTE_MTCMOS_0_CLR, MMVOTE_MTCMOS_0_DONE,
 303                 MMVOTE_MTCMOS_0_PM_ACK, DISP0_VOTE_BIT
 304         },
 305         [MTCMOS_ID_DIS1_SHUTDOWN] = {
 306                 MMVOTE_MTCMOS_0_SET, MMVOTE_MTCMOS_0_CLR, MMVOTE_MTCMOS_0_DONE,
 307                 MMVOTE_MTCMOS_0_PM_ACK, DISP1_VOTE_BIT
 308         },
 309         [MTCMOS_ID_OVL0_SHUTDOWN] = {
 310                 MMVOTE_MTCMOS_0_SET, MMVOTE_MTCMOS_0_CLR, MMVOTE_MTCMOS_0_DONE,
 311                 MMVOTE_MTCMOS_0_PM_ACK, OVL0_VOTE_BIT
 312         },
 313         [MTCMOS_ID_OVL1_SHUTDOWN] = {
 314                 MMVOTE_MTCMOS_0_SET, MMVOTE_MTCMOS_0_CLR, MMVOTE_MTCMOS_0_DONE,
 315                 MMVOTE_MTCMOS_0_PM_ACK, OVL1_VOTE_BIT
 316         },
 317         [MTCMOS_ID_DISP_EDPTX_SHUTDOWN] = {
 318                 MMVOTE_MTCMOS_0_SET, MMVOTE_MTCMOS_0_CLR, MMVOTE_MTCMOS_0_DONE,
 319                 MMVOTE_MTCMOS_0_PM_ACK, DISP_EDPTX_VOTE_BIT
 320         },
 321         [MTCMOS_ID_DISP_DPTX_SHUTDOWN] = {
 322                 MMVOTE_MTCMOS_0_SET, MMVOTE_MTCMOS_0_CLR, MMVOTE_MTCMOS_0_DONE,
 323                 MMVOTE_MTCMOS_0_PM_ACK, DISP_DPTX_VOTE_BIT
 324         },
 325         [MTCMOS_ID_MM_INFRA0] = {
 326                 MMINFRA_MTCMOS_1_SET, MMINFRA_MTCMOS_1_CLR, MMVOTE_MTCMOS_1_DONE,
 327                 MMVOTE_MTCMOS_1_PM_ACK, MMINFRA0_VOTE_BIT
 328         },
 329         [MTCMOS_ID_MM_INFRA1] = {
 330                 MMINFRA_MTCMOS_1_SET, MMINFRA_MTCMOS_1_CLR, MMVOTE_MTCMOS_1_DONE,
 331                 MMVOTE_MTCMOS_1_PM_ACK, MMINFRA1_VOTE_BIT
 332         },
 333         [MTCMOS_ID_MM_INFRA_AO] = {
 334                 MMINFRA_MTCMOS_1_SET, MMINFRA_MTCMOS_1_CLR, MMVOTE_MTCMOS_1_DONE,
 335                 MMVOTE_MTCMOS_1_PM_ACK, MMINFRA_AO_VOTE_BIT
 336         },
 337         [MTCMOS_ID_DSI_PHY0] = {
 338                 MMVOTE_MTCMOS_1_SET, MMVOTE_MTCMOS_1_CLR, MMVOTE_MTCMOS_1_DONE,
 339                 MMVOTE_MTCMOS_1_PM_ACK, DSI_PHY0_VOTE_BIT
 340         },
 341         [MTCMOS_ID_DSI_PHY1] = {
 342                 MMVOTE_MTCMOS_1_SET, MMVOTE_MTCMOS_1_CLR, MMVOTE_MTCMOS_1_DONE,
 343                 MMVOTE_MTCMOS_1_PM_ACK, DSI_PHY1_VOTE_BIT
 344         },
 345         [MTCMOS_ID_DSI_PHY2] = {
 346                 MMVOTE_MTCMOS_1_SET, MMVOTE_MTCMOS_1_CLR, MMVOTE_MTCMOS_1_DONE,
 347                 MMVOTE_MTCMOS_1_PM_ACK, DSI_PHY2_VOTE_BIT
 348         },
 349 };
 350
 351 int mtcmos_cb_register(enum mtcmos_id id, const struct mtcmos_cb *cb)
 352 {
 353         if (id >= MTCMOS_ID_NUM) {
 354                 printk(BIOS_ERR, "id(%d) is invalid\n", id);
 355                 return -1;
 356         }
 357
 358         if (id <= MTCMOS_ID_SSRSYS)
 359                 mds[id].cb = cb;
 360         else
 361                 vote_mds[id].cb = cb;
 362
 363         return 0;
 364 }
 365
 366 static int mtcmos_wait_for_state(u32 *reg, u32 mask, bool onoff)
 367 {
 368         u32 expect = onoff ? mask : 0;
 369
 370         if (!retry(ACK_DELAY_TIMES, (read32(reg) & mask) == expect, udelay(ACK_DELAY_US))) {
 371                 printk(BIOS_ERR, "%s(%p, %#x, %d) reg_val=%#x timeout\n",
 372                        __func__, reg, mask, onoff, read32(reg));
 373                 return -1;
 374         }
 375
 376         return 0;
 377 }
 378
 379 static int mtcmos_bus_prot_ctrl(const struct mtcmos_bus_prot *bp_table, bool set)
 380 {
 381         u32 *ctrl_addr;
 382         u32 mask = BIT(bp_table->bit);
 383
 384         if (set)
 385                 ctrl_addr = bp_table->bp_en_set;
 386         else
 387                 ctrl_addr = bp_table->bp_en_clr;
 388
 389         write32(ctrl_addr, mask);
 390
 391         if (set)
 392                 return mtcmos_wait_for_state(bp_table->bp_rdy, mask, set);
 393
 394         return 0;
 395 }
 396
 397 static int mtcmos_setclr_bus_prot(const struct mtcmos_bus_prot *bp_table, u32 bp_num, bool set)
 398 {
 399         int step_idx;
 400         int ret;
 401         int i;
 402
 403         for (i = 0; i < bp_num; i++) {
 404                 step_idx = set ? i : bp_num - 1 - i;
 405                 ret = mtcmos_bus_prot_ctrl(&bp_table[step_idx], set);
 406                 if (ret) {
 407                         printk(BIOS_ERR, "mtcmos_bus_prot_ctrl set fail: %d\n", ret);
 408                         mtcmos_bus_prot_ctrl(&bp_table[step_idx], !set);
 409                         return ret;
 410                 }
 411         }
 412
 413         return 0;
 414 }
 415
 416 static int mtcmos_sram_on(enum mtcmos_id id, const struct mtcmos_data *md)
 417 {
 418         u32 *ctl_addr = md->ctl_addr;
 419         int ret = 0;
 420
 421         if (MTK_SCPD_CAPS(md, MTK_SCPD_SRAM_SLP)) {
 422                 setbits32(ctl_addr, SRAM_SLP);
 423                 ret = mtcmos_wait_for_state(ctl_addr, SRAM_SLP_ACK, true);
 424         } else {
 425                 clrbits32(ctl_addr, SRAM_PDN);
 426                 ret = mtcmos_wait_for_state(ctl_addr, SRAM_PDN_ACK, false);
 427         }
 428         if (ret)
 429                 return ret;
 430
 431         if (MTK_SCPD_CAPS(md, MTK_SCPD_SRAM_ISO)) {
 432                 setbits32(ctl_addr, SRAM_ISOINT_B);
 433                 udelay(1);
 434                 clrbits32(ctl_addr, SRAM_CKISO);
 435         }
 436
 437         return 0;
 438 }
 439
 440 static int mtcmos_sram_off(enum mtcmos_id id, const struct mtcmos_data *md)
 441 {
 442         u32 *ctl_addr = md->ctl_addr;
 443
 444         if (MTK_SCPD_CAPS(md, MTK_SCPD_SRAM_ISO)) {
 445                 setbits32(ctl_addr, SRAM_CKISO);
 446                 clrbits32(ctl_addr, SRAM_ISOINT_B);
 447                 udelay(1);
 448         }
 449
 450         if (MTK_SCPD_CAPS(md, MTK_SCPD_SRAM_SLP)) {
 451                 clrbits32(ctl_addr, SRAM_SLP);
 452                 return mtcmos_wait_for_state(ctl_addr, SRAM_SLP_ACK, false);
 453         } else {
 454                 setbits32(ctl_addr, SRAM_PDN);
 455                 return mtcmos_wait_for_state(ctl_addr, SRAM_PDN_ACK, true);
 456         }
 457 }
 458
 459 static int mtcmos_onoff(enum mtcmos_id id, enum mtcmos_state state)
 460 {
 461         const struct mtcmos_data *md = &mds[id];
 462         u32 *ctl_addr = md->ctl_addr;
 463         int ret = 0;
 464
 465         if (state == MTCMOS_POWER_DOWN) {
 466                 if (md->cb && md->cb->pre_off) {
 467                         ret = md->cb->pre_off();
 468                         if (ret) {
 469                                 printk(BIOS_ERR, "mtcmos(%d) call pre_off fail(%d)\n", id, ret);
 470                                 return ret;
 471                         }
 472                 }
 473
 474                 ret = mtcmos_setclr_bus_prot(md->bp_table, md->bp_num, SET_BUS_PROTECT);
 475                 if (ret)
 476                         return ret;
 477
 478                 if (!MTK_SCPD_CAPS(md, MTK_SCPD_NO_SRAM)) {
 479                         ret = mtcmos_sram_off(id, md);
 480                         if (ret)
 481                                 return ret;
 482                 }
 483
 484                 setbits32(ctl_addr, PWR_ISO);
 485                 setbits32(ctl_addr, PWR_CLK_DIS);
 486                 clrbits32(ctl_addr, PWR_RST_B);
 487                 clrbits32(ctl_addr, PWR_ON);
 488                 ret = mtcmos_wait_for_state(ctl_addr, PWR_ACK, state);
 489                 if (ret)
 490                         return ret;
 491
 492                 clrbits32(ctl_addr, PWR_ON_2ND);
 493                 ret = mtcmos_wait_for_state(ctl_addr, PWR_ACK_2ND, state);
 494                 if (ret)
 495                         return ret;
 496
 497                 if (md->cb && md->cb->post_off) {
 498                         ret = md->cb->post_off();
 499                         if (ret) {
 500                                 printk(BIOS_ERR, "mtcmos(%d) call post_off fail(%d)\n", id, ret);
 501                                 return ret;
 502                         }
 503                 }
 504         } else {
 505                 if (md->cb && md->cb->pre_on) {
 506                         ret = md->cb->pre_on();
 507                         if (ret) {
 508                                 printk(BIOS_ERR, "mtcmos(%d) call pre_on fail(%d)\n", id, ret);
 509                                 return ret;
 510                         }
 511                 }
 512
 513                 setbits32(ctl_addr, PWR_ON);
 514                 ret = mtcmos_wait_for_state(ctl_addr, PWR_ACK, state);
 515                 if (ret)
 516                         return ret;
 517                 udelay(50);
 518
 519                 setbits32(ctl_addr, PWR_ON_2ND);
 520                 ret = mtcmos_wait_for_state(ctl_addr, PWR_ACK_2ND, state);
 521                 if (ret)
 522                         return ret;
 523
 524                 clrbits32(ctl_addr, PWR_CLK_DIS);
 525                 clrbits32(ctl_addr, PWR_ISO);
 526
 527                 if (MTK_SCPD_CAPS(md, MTK_SCPD_RTFF_DELAY))
 528                         udelay(10);
 529
 530                 setbits32(ctl_addr, PWR_RST_B);
 531                 if (!MTK_SCPD_CAPS(md, MTK_SCPD_NO_SRAM)) {
 532                         ret = mtcmos_sram_on(id, md);
 533                         if (ret)
 534                                 return ret;
 535                 }
 536
 537                 ret = mtcmos_setclr_bus_prot(md->bp_table, md->bp_num, RELEASE_BUS_PROTECT);
 538                 if (ret)
 539                         return ret;
 540
 541                 if (md->cb && md->cb->post_on) {
 542                         ret = md->cb->post_on();
 543                         if (ret) {
 544                                 printk(BIOS_ERR, "mtcmos(%d) call post_on fail(%d)\n", id, ret);
 545                                 return ret;
 546                         }
 547                 }
 548         }
 549
 550         return 0;
 551 }
 552
 553 static int mtcmos_vote_onoff(enum mtcmos_id id, enum mtcmos_state state)
 554 {
 555         const struct mtcmos_vote_data *md = &vote_mds[id];
 556         u32 vote_bit = BIT(md->vote_bit);
 557         int ret = 0;
 558
 559         if (state == MTCMOS_POWER_DOWN) {
 560                 if (md->cb && md->cb->pre_off) {
 561                         ret = md->cb->pre_off();
 562                         if (ret) {
 563                                 printk(BIOS_ERR, "mtcmos(%d) call pre_off fail(%d)\n", id, ret);
 564                                 return ret;
 565                         }
 566                 }
 567
 568                 write32(md->clr_addr, vote_bit);
 569                 if (!wait_us(WAIT_VOTE_TIMEOUT, ((read32(md->done_addr) & vote_bit) != 0 &&
 570                                                  (read32(md->ack_addr) & vote_bit) == vote_bit))) {
 571                         printk(BIOS_ERR, "mtcmos_vote disable %d timeout\n", id);
 572                         return -1;
 573                 }
 574
 575                 if (md->cb && md->cb->post_off) {
 576                         ret = md->cb->post_off();
 577                         if (ret) {
 578                                 printk(BIOS_ERR, "mtcmos(%d) call post_off fail(%d)\n", id, ret);
 579                                 return ret;
 580                         }
 581                 }
 582         } else {
 583                 if (md->cb && md->cb->pre_on) {
 584                         ret = md->cb->pre_on();
 585                         if (ret) {
 586                                 printk(BIOS_ERR, "mtcmos(%d) call pre_on fail(%d)\n", id, ret);
 587                                 return ret;
 588                         }
 589                 }
 590
 591                 write32(md->set_addr, vote_bit);
 592                 if (!wait_us(WAIT_VOTE_TIMEOUT, ((read32(md->done_addr) & vote_bit) != 0 &&
 593                                                  (read32(md->ack_addr) & vote_bit) == vote_bit))) {
 594                         printk(BIOS_ERR, "mtcmos_vote enable %d timeout\n", id);
 595                         return ret;
 596                 }
 597
 598                 if (md->cb && md->cb->post_on) {
 599                         ret = md->cb->post_on();
 600                         if (ret) {
 601                                 printk(BIOS_ERR, "mtcmos(%d) call post_on fail(%d)\n", id, ret);
 602                                 return ret;
 603                         }
 604                 }
 605         }
 606
 607         return 0;
 608 }
 609
 610 static void mtcmos_spm_clr_rtff_flag(void)
 611 {
 612         clrbits32(&mtk_spm_mtcmos->conn_pwr_con, PWR_RTFF_SAVE_FLAG);
 613         clrbits32(&mtk_spm_mtcmos->ssusb_dp_phy_p0_pwr_con, PWR_RTFF_SAVE_FLAG);
 614         clrbits32(&mtk_spm_mtcmos->ssusb_p0_pwr_con, PWR_RTFF_SAVE_FLAG);
 615         clrbits32(&mtk_spm_mtcmos->ssusb_p1_pwr_con, PWR_RTFF_SAVE_FLAG);
 616         clrbits32(&mtk_spm_mtcmos->ssusb_p23_pwr_con, PWR_RTFF_SAVE_FLAG);
 617         clrbits32(&mtk_spm_mtcmos->ssusb_phy_p2_pwr_con, PWR_RTFF_SAVE_FLAG);
 618         clrbits32(&mtk_spm_mtcmos->ufs0_pwr_con, PWR_RTFF_SAVE_FLAG);
 619         clrbits32(&mtk_spm_mtcmos->ufs0_phy_pwr_con, PWR_RTFF_SAVE_FLAG);
 620         clrbits32(&mtk_spm_mtcmos->pextp_mac0_pwr_con, PWR_RTFF_SAVE_FLAG);
 621         clrbits32(&mtk_spm_mtcmos->pextp_mac1_pwr_con, PWR_RTFF_SAVE_FLAG);
 622         clrbits32(&mtk_spm_mtcmos->pextp_mac2_pwr_con, PWR_RTFF_SAVE_FLAG);
 623         clrbits32(&mtk_spm_mtcmos->pextp_phy0_pwr_con, PWR_RTFF_SAVE_FLAG);
 624         clrbits32(&mtk_spm_mtcmos->pextp_phy1_pwr_con, PWR_RTFF_SAVE_FLAG);
 625         clrbits32(&mtk_spm_mtcmos->pextp_phy2_pwr_con, PWR_RTFF_SAVE_FLAG);
 626         clrbits32(&mtk_spm_mtcmos->audio_pwr_con, PWR_RTFF_SAVE_FLAG);
 627         clrbits32(&mtk_spm_mtcmos->adsp_infra_pwr_con, PWR_RTFF_SAVE_FLAG);
 628         clrbits32(&mtk_spm_mtcmos->adsp_ao_pwr_con, PWR_RTFF_SAVE_FLAG);
 629         clrbits32(&mtk_spm_mtcmos->mm_proc_pwr_con, PWR_RTFF_SAVE_FLAG);
 630         clrbits32(&mtk_spm_mtcmos->ssrsys_pwr_con, PWR_RTFF_SAVE_FLAG);
 631         clrbits32(&mtk_spm_mtcmos->spu_ise_pwr_con, PWR_RTFF_SAVE_FLAG);
 632         clrbits32(&mtk_spm_mtcmos->spu_hwrot_pwr_con, PWR_RTFF_SAVE_FLAG);
 633         clrbits32(&mtk_spm_mtcmos->hsgmii0_pwr_con, PWR_RTFF_SAVE_FLAG);
 634         clrbits32(&mtk_spm_mtcmos->hsgmii1_pwr_con, PWR_RTFF_SAVE_FLAG);
 635 }
 636
 637 static int mtcmos_disp_vcore_pre_on(void)
 638 {
 639         write32(MM_BUCK_ISO_CON_CLR, BIT(0));
 640         write32(MM_BUCK_ISO_CON_CLR, BIT(1));
 641         write32(MM_BUCK_ISO_CON_CLR, BIT(2));
 642
 643         write32(DISP_AO_PWR_CON, 0x1);
 644
 645         return 0;
 646 }
 647
 648 static int mtcmos_disp_vcore_post_on(void)
 649 {
 650         write32(MMPC_BUS_PROTECT_EN_1_CLR, BIT(6) | BIT(7));
 651
 652         write32p(DISP_VDISP_AO_CONFIG_CG, 0xFFFFFFFF);
 653
 654         setbits32p(DISP_DPC_DISP0_MTCMOS_CFG, BIT(4));
 655         setbits32p(DISP_DPC_DISP1_MTCMOS_CFG, BIT(4));
 656         setbits32p(DISP_DPC_OVL0_MTCMOS_CFG, BIT(4));
 657         setbits32p(DISP_DPC_OVL1_MTCMOS_CFG, BIT(4));
 658         setbits32p(DISP_DPC_MML0_MTCMOS_CFG, BIT(4));
 659         setbits32p(DISP_DPC_MML1_MTCMOS_CFG, BIT(4));
 660         setbits32p(DISP_DPC_EDP_MTCMOS_CFG, BIT(4));
 661         setbits32p(DISP_DPC_EPTX_MTCMOS_CFG, BIT(4));
 662
 663         return 0;
 664 }
 665
 666 static struct mtcmos_cb disp_vcore_cb = {
 667         .pre_on = mtcmos_disp_vcore_pre_on,
 668         .post_on = mtcmos_disp_vcore_post_on,
 669 };
 670
 671 void mtcmos_protect_display_bus(void)
 672 {
 673         /* empty implementation for user common flow */
 674 }
 675
 676 void mtcmos_display_power_on(void)
 677 {
 678         mtcmos_ctrl(MTCMOS_ID_DIS0_SHUTDOWN, MTCMOS_POWER_ON);
 679         mtcmos_ctrl(MTCMOS_ID_DIS1_SHUTDOWN, MTCMOS_POWER_ON);
 680         mtcmos_ctrl(MTCMOS_ID_OVL0_SHUTDOWN, MTCMOS_POWER_ON);
 681         mtcmos_ctrl(MTCMOS_ID_OVL1_SHUTDOWN, MTCMOS_POWER_ON);
 682         mtcmos_ctrl(MTCMOS_ID_DISP_EDPTX_SHUTDOWN, MTCMOS_POWER_ON);
 683         mtcmos_ctrl(MTCMOS_ID_DISP_DPTX_SHUTDOWN, MTCMOS_POWER_ON);
 684 }
 685
 686 void mtcmos_ctrl(enum mtcmos_id id, enum mtcmos_state state)
 687 {
 688         int ret = 0;
 689
 690         if (id >= MTCMOS_ID_NUM) {
 691                 printk(BIOS_ERR, "id(%d) is invalid\n", id);
 692                 return;
 693         }
 694
 695         if (id <= MTCMOS_ID_SSRSYS)
 696                 ret = mtcmos_onoff(id, state);
 697         else
 698                 ret = mtcmos_vote_onoff(id, state);
 699
 700         if (ret)
 701                 printk(BIOS_ERR, "%s(%u, %u) fail, ret=%d\n", __func__, id, state, ret);
 702 }
 703
 704 void mtcmos_init(void)
 705 {
 706         write32(POWERON_CONFIG_EN, (SPM_PROJECT_CODE << 16) | BIT(0));
 707
 708         mtcmos_spm_clr_rtff_flag();
 709
 710         mtcmos_ctrl(MTCMOS_ID_SSUSB_P0, MTCMOS_POWER_ON);
 711         mtcmos_ctrl(MTCMOS_ID_SSUSB_DP_PHY_P0, MTCMOS_POWER_ON);
 712         mtcmos_ctrl(MTCMOS_ID_SSUSB_P1, MTCMOS_POWER_ON);
 713         mtcmos_ctrl(MTCMOS_ID_SSUSB_P23, MTCMOS_POWER_ON);
 714         mtcmos_ctrl(MTCMOS_ID_SSUSB_PHY_P2, MTCMOS_POWER_ON);
 715         mtcmos_ctrl(MTCMOS_ID_UFS0_SHUTDOWN, MTCMOS_POWER_ON);
 716         mtcmos_ctrl(MTCMOS_ID_UFS0_PHY, MTCMOS_POWER_ON);
 717         mtcmos_ctrl(MTCMOS_ID_PEXTP_MAC0, MTCMOS_POWER_ON);
 718         mtcmos_ctrl(MTCMOS_ID_PEXTP_MAC1, MTCMOS_POWER_ON);
 719         mtcmos_ctrl(MTCMOS_ID_PEXTP_MAC2, MTCMOS_POWER_ON);
 720         mtcmos_ctrl(MTCMOS_ID_PEXTP_PHY0, MTCMOS_POWER_ON);
 721         mtcmos_ctrl(MTCMOS_ID_PEXTP_PHY1, MTCMOS_POWER_ON);
 722         mtcmos_ctrl(MTCMOS_ID_PEXTP_PHY2, MTCMOS_POWER_ON);
 723         mtcmos_ctrl(MTCMOS_ID_ADSP_TOP_SHUTDOWN, MTCMOS_POWER_DOWN);
 724         mtcmos_ctrl(MTCMOS_ID_AUDIO, MTCMOS_POWER_DOWN);
 725         mtcmos_ctrl(MTCMOS_ID_ADSP_INFRA, MTCMOS_POWER_DOWN);
 726         mtcmos_ctrl(MTCMOS_ID_ADSP_AO, MTCMOS_POWER_DOWN);
 727         mtcmos_ctrl(MTCMOS_ID_ADSP_AO, MTCMOS_POWER_ON);
 728         mtcmos_ctrl(MTCMOS_ID_ADSP_INFRA, MTCMOS_POWER_ON);
 729         mtcmos_ctrl(MTCMOS_ID_AUDIO, MTCMOS_POWER_ON);
 730         mtcmos_ctrl(MTCMOS_ID_ADSP_TOP_SHUTDOWN, MTCMOS_POWER_ON);
 731         mtcmos_ctrl(MTCMOS_ID_MM_PROC_SHUTDOWN, MTCMOS_POWER_ON);
 732         mtcmos_ctrl(MTCMOS_ID_SSRSYS, MTCMOS_POWER_ON);
 733 }
 734
 735 void mtcmos_post_init(void)
 736 {
 737         if (mtcmos_cb_register(MTCMOS_ID_DISP_VCORE, &disp_vcore_cb))
 738                 printk(BIOS_ERR, "register disp_vcore failed\n");
 739
 740         mtcmos_ctrl(MTCMOS_ID_MM_INFRA_AO, MTCMOS_POWER_ON);
 741         mtcmos_ctrl(MTCMOS_ID_MM_INFRA0, MTCMOS_POWER_ON);
 742         mtcmos_ctrl(MTCMOS_ID_MM_INFRA1, MTCMOS_POWER_ON);
 743
 744         mtcmos_ctrl(MTCMOS_ID_DISP_VCORE, MTCMOS_POWER_ON);
 745         write32(&mtk_disp->clk_cfg[0].clr, 0x00000007);
 746
 747         mtcmos_ctrl(MTCMOS_ID_DIS0_SHUTDOWN, MTCMOS_POWER_ON);
 748         write32(&mtk_mmsys->clk_cfg[0].clr, 0xFFFFFFFF);
 749         write32(&mtk_mmsys->clk_cfg[1].clr, 0x07FFFFFF);
 750
 751         mtcmos_ctrl(MTCMOS_ID_DIS1_SHUTDOWN, MTCMOS_POWER_ON);
 752         write32(&mtk_mmsys1->clk_cfg[0].clr, 0xFFFFFFFF);
 753         write32(&mtk_mmsys1->clk_cfg[1].clr, 0x1FF3FFFF);
 754
 755         mtcmos_ctrl(MTCMOS_ID_OVL0_SHUTDOWN, MTCMOS_POWER_ON);
 756         write32(&mtk_ovlsys->clk_cfg[0].clr, 0xFFFFFFFF);
 757         write32(&mtk_ovlsys->clk_cfg[1].clr, 0x7FFFFFFF);
 758
 759         mtcmos_ctrl(MTCMOS_ID_OVL1_SHUTDOWN, MTCMOS_POWER_ON);
 760         write32(&mtk_ovlsys1->clk_cfg[0].clr, 0xFFFFFFFF);
 761         write32(&mtk_ovlsys1->clk_cfg[1].clr, 0x7FFFFFFF);
 762
 763         mtcmos_ctrl(MTCMOS_ID_DISP_EDPTX_SHUTDOWN, MTCMOS_POWER_ON);
 764         mtcmos_ctrl(MTCMOS_ID_DISP_DPTX_SHUTDOWN, MTCMOS_POWER_ON);
 765         mtcmos_ctrl(MTCMOS_ID_DSI_PHY0, MTCMOS_POWER_ON);
 766         mtcmos_ctrl(MTCMOS_ID_DSI_PHY1, MTCMOS_POWER_ON);
 767         mtcmos_ctrl(MTCMOS_ID_DSI_PHY2, MTCMOS_POWER_ON);
 768
 769         /* vmm buck isolation off */
 770         write32(MM_BUCK_ISO_CON_CLR, BIT(4));
 771         write32(MM_BUCK_ISO_CON_CLR, BIT(5));
 772         write32(MM_BUCK_ISO_CON_CLR, BIT(6));
 773 }