soc/intel/xeon_sp: Allow OS to control LTR and AER
[coreboot2.git] / src / soc / mediatek / mt8196 / mtk_pwrsel.c
blobb1cb52865cebb0d4fa4a856b58b0d13e067ed280
1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
3 #include <console/console.h>
4 #include <device/mmio.h>
5 #include <soc/mtk_pwrsel.h>
7 static void cpu_pwrsel_init(void)
9 write32p(MCUSYS_BASE + OFFSET_PWRSEL, VAL_PWRSEL);
10 write32p(MCUSYS_BASE + OFFSET_PWRSEL_AUTO_MODE_CFG, VAL_PWRSEL_AUTO_MODE);
13 static void gpu_pwrsel_init(void)
15 write32p(MFG_VCORE_AO_RPC_PWRSEL_CONFIG, GENMASK(14, 0));
18 void pwrsel_init(void)
20 cpu_pwrsel_init();
21 gpu_pwrsel_init();
23 /* PWR_SEL must be 0x0 */
24 printk(BIOS_DEBUG, "PWR_SEL = %#x\n", read32p(MCUSYS_BASE + OFFSET_PWRSEL));
25 /* PWRSEL_CONFIG must be 0x7fff */
26 printk(BIOS_DEBUG, "PWRSEL_CONFIG = %#x\n", read32p(MFG_VCORE_AO_RPC_PWRSEL_CONFIG));