src/soc/mediatek/mt8196/pmif_spmi.c

   1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
   2
   3 #include <console/console.h>
   4 #include <device/mmio.h>
   5 #include <gpio.h>
   6 #include <soc/addressmap.h>
   7 #include <soc/pll.h>
   8 #include <soc/pmif.h>
   9 #include <soc/pmif_spmi.h>
  10 #include <soc/spmi.h>
  11
  12 #define SPMI_RCS_CTRL_BASE 0x140084
  13
  14 /* TOPCKGEN, CLK_CFG_17 */
  15 DEFINE_BITFIELD(CLK_SPMI_MST_SEL, 10, 8)
  16 DEFINE_BIT(CLK_SPMI_MST_INT, 12)
  17 DEFINE_BIT(PDN_SPMI_MST, 15)
  18
  19 /* TOPCKGEN, CLK_CFG_UPDATE2 */
  20 DEFINE_BIT(SPMI_MST_CK_UPDATE, 5)
  21
  22 /* SPMI_MST, SPMI_SAMPL_CTRL */
  23 DEFINE_BIT(SAMPL_CK_POL, 0)
  24 DEFINE_BITFIELD(SAMPL_CK_DLY, 3, 1)
  25 DEFINE_BITFIELD(SAMPL_CK_DLY_ARB, 6, 4)
  26
  27 /* PMIF, SPI_MODE_CTRL */
  28 DEFINE_BIT(VLD_SRCLK_EN_CTRL, 5)
  29 DEFINE_BIT(SPI_MODE_CTRL_PMIF_RDY, 9)
  30 DEFINE_BIT(SPI_MODE_CTRL_SRCLK_EN, 10)
  31 DEFINE_BIT(SPI_MODE_CTRL_SRVOL_EN, 11)
  32
  33 /* PMIF, SLEEP_PROTECTION_CTRL */
  34 DEFINE_BIT(SPM_SLEEP_REQ_SEL, 0)
  35 DEFINE_BIT(SCP_SLEEP_REQ_SEL, 9)
  36
  37 const struct spmi_device spmi_dev[] = {
  38         {
  39                 .slvid = SPMI_SLAVE_4,  /* MT6363 */
  40                 .mstid = SPMI_MASTER_1,
  41                 .type = MAIN_PMIC,
  42                 .type_id = MAIN_PMIC_ID,
  43                 .hwcid_addr = 0x09,
  44                 .hwcid_val = 0x63,
  45                 .hwcid_mask = 0xF0,
  46         },
  47         {
  48                 .slvid = SPMI_SLAVE_9,  /* MT6685 */
  49                 .mstid = SPMI_MASTER_1,
  50                 .type = CLOCK_PMIC,
  51                 .type_id = CLOCK_PMIC_ID,
  52                 .hwcid_addr = 0x09,
  53                 .hwcid_val = 0x85,
  54                 .hwcid_mask = 0xF0,
  55         },
  56         {
  57                 .slvid = SPMI_SLAVE_5, /* MT6373 */
  58                 .mstid = SPMI_MASTER_1,
  59                 .type = SECOND_PMIC,
  60                 .type_id = SECOND_PMIC_ID,
  61                 .hwcid_addr = 0x09,
  62                 .hwcid_val = 0x73,
  63                 .hwcid_mask = 0xF0,
  64         },
  65         {
  66                 .slvid = SPMI_SLAVE_6,  /* MT6316 */
  67                 .mstid = SPMI_MASTER_0,
  68                 .type = SUB_PMIC,
  69                 .type_id = SUB_PMIC_ID,
  70                 .hwcid_addr = 0x209,
  71                 .hwcid_val = 0x16,
  72                 .hwcid_mask = 0xf0,
  73         },
  74         {
  75                 .slvid = SPMI_SLAVE_7,  /* MT6316 */
  76                 .mstid = SPMI_MASTER_0,
  77                 .type = SUB_PMIC,
  78                 .type_id = SUB_PMIC_ID,
  79                 .hwcid_addr = 0x209,
  80                 .hwcid_val = 0x16,
  81                 .hwcid_mask = 0xf0,
  82         },
  83         {
  84                 .slvid = SPMI_SLAVE_8,  /* MT6316 */
  85                 .mstid = SPMI_MASTER_0,
  86                 .type = SUB_PMIC,
  87                 .type_id = SUB_PMIC_ID,
  88                 .hwcid_addr = 0x209,
  89                 .hwcid_val = 0x16,
  90                 .hwcid_mask = 0xf0,
  91         },
  92         {
  93                 .slvid = SPMI_SLAVE_15,  /* MT6316 */
  94                 .mstid = SPMI_MASTER_0,
  95                 .type = SUB_PMIC,
  96                 .type_id = SUB_PMIC_ID,
  97                 .hwcid_addr = 0x209,
  98                 .hwcid_val = 0x16,
  99                 .hwcid_mask = 0xf0,
 100         },
 101 };
 102
 103 static const uint32_t chan_perm[2][4] = {
 104         [SPMI_MASTER_0] = { 0x8888888A, 0x88888888, 0x88888888, 0x88888888 },
 105         [SPMI_MASTER_1] = { 0x888888AA, 0x88888888, 0x88888888, 0x88888888 },
 106 };
 107
 108 static const uint32_t lat_limit[2][23] = {
 109         [SPMI_MASTER_0] = { 0x3e6, 0x3e6, 0x9, 0x9, 0x3e6, 0x3e6, 0x3e6, 0x3e6, 0x9, 0x3e6,
 110                             0x0, 0x3e6, 0x9, 0x0, 0x0, 0x3e6, 0x3e6, 0x3e6, 0x3e6, 0x0,
 111                             0x3e6, 0x0, 0x3e6 },
 112         [SPMI_MASTER_1] = { 0x3e6, 0x0, 0x3e6, 0x3e6, 0x26, 0x37, 0x3e6, 0x10, 0x9, 0x23,
 113                             0x0, 0x39, 0x9, 0x0, 0x0, 0x12, 0x3e6, 0x3e6, 0x3e6, 0x0,
 114                             0x1e, 0x0, 0x3e6 },
 115 };
 116
 117 const size_t spmi_dev_cnt = ARRAY_SIZE(spmi_dev);
 118
 119 static struct mtk_spmi_mst_reg *get_mst_reg(struct pmif *arb)
 120 {
 121         if (arb->mstid == SPMI_MASTER_1)
 122                 return mtk_spmi_mst;
 123         else if (arb->mstid == SPMI_MASTER_0 || arb->mstid == SPMI_MASTER_2)
 124                 return mtk_spmi_mst_p;
 125         else
 126                 return NULL;
 127 }
 128
 129 static int pmif_spmi_config_master(struct pmif *arb)
 130 {
 131         struct mtk_spmi_mst_reg *reg = get_mst_reg(arb);
 132         if (!reg) {
 133                 printk(BIOS_ERR, "%s: get_mst_reg get null pointer\n", __func__);
 134                 return -1;
 135         }
 136
 137         write32(&reg->mst_req_en, 1);
 138         write32(&reg->grp_id_en, 0xC00);
 139         /* enable multi-master and rcs support */
 140         write32(&reg->rcs_ctrl, SPMI_RCS_CTRL_BASE + arb->mstid);
 141         printk(BIOS_INFO, "%s: mstid=%d done\n", __func__, arb->mstid);
 142         return 0;
 143 }
 144
 145 void pmif_spmi_config(struct pmif *arb)
 146 {
 147         _Static_assert(ARRAY_SIZE(chan_perm[0]) == ARRAY_SIZE(arb->mtk_pmif->inf_cmd_per),
 148                        "Inconsistent array size for chan_perm and inf_cmd_per");
 149         const uint32_t *perm = chan_perm[arb->mstid % 2];
 150         /*
 151          * all cmd permission for per channel
 152          * [0]: Command 0 Permitted
 153          * [1]: Command 1 Permitted
 154          * [2]: Command 2 Permitted
 155          * [3]: Command 3 Permitted
 156          */
 157         /* PER_0[8:0]: CH0 or CH1 for MD DVFS HW, backward compatible for swrgo */
 158         for (int i = 0; i < ARRAY_SIZE(arb->mtk_pmif->inf_cmd_per); i++)
 159                 write32(&arb->mtk_pmif->inf_cmd_per[i], perm[i]);
 160 }
 161
 162 void pmif_spmi_iocfg(void)
 163 {
 164         /* SPMI_M 10mA */
 165         gpio_set_driving(GPIO(SPMI_M_SCL), GPIO_DRV_10_MA);
 166         gpio_set_driving(GPIO(SPMI_M_SDA), GPIO_DRV_10_MA);
 167         /* SPMI_P 14mA */
 168         gpio_set_driving(GPIO(SPMI_P_SCL), GPIO_DRV_14_MA);
 169         gpio_set_driving(GPIO(SPMI_P_SDA), GPIO_DRV_14_MA);
 170         printk(BIOS_INFO, "%s done\n", __func__);
 171 }
 172
 173 static int spmi_read_check(struct pmif *arb, const struct spmi_device *dev)
 174 {
 175         u32 rdata = 0;
 176
 177         arb->read(arb, dev->slvid, dev->hwcid_addr, &rdata);
 178         if ((rdata & dev->hwcid_mask) != (dev->hwcid_val & dev->hwcid_mask)) {
 179                 printk(BIOS_WARNING, "%s next, slvid:%d rdata = 0x%x\n",
 180                        __func__, dev->slvid, rdata);
 181                 return -E_NODEV;
 182         }
 183
 184         printk(BIOS_INFO, "%s next, slvid:%d rdata = 0x%x.\n", __func__, dev->slvid, rdata);
 185         return 0;
 186 }
 187
 188 static int spmi_cali_rd_clock_polarity(struct pmif *arb, const struct spmi_device *dev)
 189 {
 190         size_t i;
 191         bool success = false;
 192         const struct cali cali_data[] = {
 193                 {SPMI_CK_DLY_1T, SPMI_CK_POL_NEG},
 194                 {SPMI_CK_DLY_1T, SPMI_CK_POL_POS},
 195                 {SPMI_CK_NO_DLY, SPMI_CK_POL_POS},
 196                 {SPMI_CK_NO_DLY, SPMI_CK_POL_NEG},
 197                 {SPMI_CK_DLY_2T, SPMI_CK_POL_POS},
 198                 {SPMI_CK_DLY_2T, SPMI_CK_POL_NEG},
 199         };
 200
 201         struct mtk_spmi_mst_reg *reg = get_mst_reg(arb);
 202         if (!reg) {
 203                 printk(BIOS_ERR, "%s: get_mst_reg get null pointer\n", __func__);
 204                 return -1;
 205         }
 206
 207         /* Indicate sampling clock polarity, 1: Positive 0: Negative */
 208         for (i = 0; i < ARRAY_SIZE(cali_data); i++) {
 209                 SET32_BITFIELDS(&reg->mst_sampl, SAMPL_CK_DLY, cali_data[i].dly,
 210                                 SAMPL_CK_POL, cali_data[i].pol);
 211                 SET32_BITFIELDS(&reg->mst_sampl, SAMPL_CK_DLY_ARB, cali_data[i].dly + 1);
 212                 printk(BIOS_DEBUG, "dly:%d, pol:%d, sampl:0x%x\n",
 213                        cali_data[i].dly, cali_data[i].pol, read32(&reg->mst_sampl));
 214                 if (spmi_read_check(arb, dev) == 0) {
 215                         success = true;
 216                         break;
 217                 }
 218         }
 219
 220         if (!success)
 221                 die("ERROR - calibration fail for SPMI clk");
 222
 223         return 0;
 224 }
 225
 226 static int spmi_config_slave(struct pmif *arb, const struct spmi_device *dev)
 227 {
 228         u32 wdata;
 229
 230         /* set RG_RCS_ADDR=slave id */
 231         wdata = dev->slvid;
 232         arb->write(arb, dev->slvid, 0x419, wdata); /* rcs_slvid_addr: 0x419 */
 233
 234         /* set RG_RCS_ENABLE=1, RG_RCS_ID=Master ID */
 235         wdata = 0x5 | (dev->mstid << 4);
 236         arb->write(arb, dev->slvid, 0x418, wdata); /* rcs_slvid_en: 0x418 */
 237
 238         return 0;
 239 }
 240
 241 static int spmi_mst_init(struct pmif *arb)
 242 {
 243         int i;
 244
 245         if (!arb) {
 246                 printk(BIOS_ERR, "%s: null pointer for pmif dev\n", __func__);
 247                 return -E_INVAL;
 248         }
 249
 250         if (!CONFIG(PMIF_SPMI_IOCFG_DEFAULT_SETTING))
 251                 pmif_spmi_iocfg();
 252
 253         if (pmif_spmi_config_master(arb))
 254                 return -1;
 255
 256         for (i = 0; i < spmi_dev_cnt; i++) {
 257                 if ((arb->mstid % 2) == spmi_dev[i].mstid) {
 258                         spmi_cali_rd_clock_polarity(arb, &spmi_dev[i]); /* spmi_cali */
 259                         spmi_config_slave(arb, &spmi_dev[i]);
 260                 }
 261         }
 262
 263         return 0;
 264 }
 265
 266 static void pmif_spmi_force_normal_mode(struct pmif *arb)
 267 {
 268         /* listen srclken_0 only for entering normal or sleep mode */
 269         SET32_BITFIELDS(&arb->mtk_pmif->spi_mode_ctrl,
 270                         VLD_SRCLK_EN_CTRL, 0,
 271                         SPI_MODE_CTRL_PMIF_RDY, 1,
 272                         SPI_MODE_CTRL_SRCLK_EN, 0,
 273                         SPI_MODE_CTRL_SRVOL_EN, 0);
 274
 275         /* disable spm/scp sleep request */
 276         SET32_BITFIELDS(&arb->mtk_pmif->sleep_protection_ctrl, SPM_SLEEP_REQ_SEL, 1,
 277                         SCP_SLEEP_REQ_SEL, 1);
 278         printk(BIOS_INFO, "%s done\n", __func__);
 279 }
 280
 281 static void pmif_spmi_enable_swinf(struct pmif *arb)
 282 {
 283         write32(&arb->mtk_pmif->inf_en, PMIF_SPMI_SW_CHAN);
 284         write32(&arb->mtk_pmif->arb_en, PMIF_SPMI_SW_CHAN);
 285         printk(BIOS_INFO, "%s done\n", __func__);
 286 }
 287
 288 static void pmif_spmi_enable_cmd_issue(struct pmif *arb, bool en)
 289 {
 290         /* Enable cmdIssue */
 291         write32(&arb->mtk_pmif->cmdissue_en, en);
 292         printk(BIOS_INFO, "%s done\n", __func__);
 293 }
 294
 295 static void pmif_spmi_enable(struct pmif *arb)
 296 {
 297         _Static_assert(ARRAY_SIZE(lat_limit[0]) == ARRAY_SIZE(arb->mtk_pmif->lat_limit),
 298                        "Inconsistent array size for lat_limit and arb->mtk_pmif->lat_limit");
 299         const uint32_t *lat_limit_value = lat_limit[arb->mstid % 2];
 300         u32 pmif_spmi_inf;
 301         int i;
 302
 303         if (arb->mstid % 2)
 304                 pmif_spmi_inf = PMIF_SPMI_INF;
 305         else
 306                 pmif_spmi_inf = PMIF_SPMI_INF_P;
 307
 308         pmif_spmi_config(arb);
 309
 310         /* set bytecnt max limitation, 0:1 byte, 1:2 bytes */
 311         for (i = 0; i < ARRAY_SIZE(arb->mtk_pmif->inf_max_bytecnt_per); i++)
 312                 write32(&arb->mtk_pmif->inf_max_bytecnt_per[i], 0x11111111);
 313
 314         /* Add latency limitation for all channels, method 2 */
 315         /* Latency unit = (LAT_UNIT_SEL + 1)T of TMR_CK, LAT_UNIT_SEL=25;Lat unit=26T ~=1us */
 316         write32(&arb->mtk_pmif->lat_cnter_ctrl, 0x32);
 317         if (arb->mstid % 2)
 318                 write32(&arb->mtk_pmif->lat_cnter_en, pmif_spmi_inf);
 319         for (i = 0; i < ARRAY_SIZE(arb->mtk_pmif->lat_limit); i++)
 320                 write32(&arb->mtk_pmif->lat_limit[i], lat_limit_value[i]);
 321         write32(&arb->mtk_pmif->lat_limit_loading, pmif_spmi_inf);
 322
 323         /* Disable STAUPD_ITEM_EN */
 324         write32(&arb->mtk_pmif->staupd_ctrl, 0x1030000);
 325
 326         write32(&arb->mtk_pmif->inf_en, pmif_spmi_inf);
 327         write32(&arb->mtk_pmif->arb_en, pmif_spmi_inf);
 328         write32(&arb->mtk_pmif->timer_ctrl, 0x3);
 329         write32(&arb->mtk_pmif->init_done, 1);
 330         printk(BIOS_INFO, "%s init done: 0x%x\n", __func__, read32(&arb->mtk_pmif->init_done));
 331 }
 332
 333 int pmif_spmi_init(struct pmif *arb)
 334 {
 335         if (arb->is_pmif_init_done(arb) != 0) {
 336                 pmif_spmi_force_normal_mode(arb);
 337                 pmif_spmi_enable_swinf(arb);
 338                 pmif_spmi_enable_cmd_issue(arb, true);
 339                 pmif_spmi_enable(arb);
 340                 if (arb->is_pmif_init_done(arb))
 341                         return -E_NODEV;
 342         }
 343
 344         if (spmi_mst_init(arb)) {
 345                 printk(BIOS_ERR, "[%s] failed to init SPMI master\n", __func__);
 346                 return -E_NODEV;
 347         }
 348
 349         return 0;
 350 }