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drivers/mipi: Add support for KD_KD110N11_51IE panel
[coreboot2.git] / src / soc / nvidia / tegra124 / dp.c
blobcc14c2ee4c5e3f0dfb0b679cd78b2f66cd8fe368
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 /*
4 * drivers/video/tegra/dc/dp.c
5 */
6
7 #include <console/console.h>
8 #include <delay.h>
9 #include <device/device.h>
10 #include <device/i2c_simple.h>
11 #include <edid.h>
12 #include <soc/addressmap.h>
13 #include <soc/nvidia/tegra/i2c.h>
14 #include <soc/nvidia/tegra/dc.h>
15 #include <soc/nvidia/tegra/displayport.h>
16 #include <soc/sor.h>
17 #include <string.h>
18 #include <types.h>
19
20 #include "chip.h"
21
22 enum {
23 DP_LT_SUCCESS = 0,
24 DP_LT_FAILED = -1,
25 };
26
27 struct tegra_dc_dp_data dp_data;
28
29 static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg)
30 {
31 void *addr = dp->aux_base + (u32)(reg << 2);
32 u32 reg_val = READL(addr);
33 return reg_val;
34 }
35
36 static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp,
37 u32 reg, u32 val)
38 {
39 void *addr = dp->aux_base + (u32)(reg << 2);
40 WRITEL(val, addr);
41 }
42
43 static inline u32 tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data *dp,
44 u32 reg, u32 mask, u32 exp_val,
45 u32 poll_interval_us,
46 u32 timeout_us)
47 {
48 u32 reg_val = 0;
49 u32 temp = timeout_us;
50
51 do {
52 udelay(poll_interval_us);
53 reg_val = tegra_dpaux_readl(dp, reg);
54 if (timeout_us > poll_interval_us)
55 timeout_us -= poll_interval_us;
56 else
57 break;
58 } while ((reg_val & mask) != exp_val);
59
60 if ((reg_val & mask) == exp_val)
61 return 0; /* success */
62 printk(BIOS_ERR,
63 "dpaux_poll_register 0x%x: timeout: "
64 "(reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n",
65 reg, reg_val, mask, exp_val);
66 return temp;
67 }
68
69 static inline int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp)
70 {
71 /* According to DP spec, each aux transaction needs to finish
72 within 40ms. */
73 if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL,
74 DPAUX_DP_AUXCTL_TRANSACTREQ_MASK,
75 DPAUX_DP_AUXCTL_TRANSACTREQ_DONE,
76 100, DP_AUX_TIMEOUT_MS * 1000) != 0) {
77 printk(BIOS_INFO, "dp: DPAUX transaction timeout\n");
78 return -1;
79 }
80 return 0;
81 }
82
83 static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
84 u32 addr, u8 *data, u32 *size,
85 u32 *aux_stat)
86 {
87 int i;
88 u32 reg_val;
89 u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
90 u32 defer_retries = DP_AUX_DEFER_MAX_TRIES;
91 u32 temp_data;
92
93 if (*size > DP_AUX_MAX_BYTES)
94 return -1; /* only write one chunk of data */
95
96 /* Make sure the command is write command */
97 switch (cmd) {
98 case DPAUX_DP_AUXCTL_CMD_I2CWR:
99 case DPAUX_DP_AUXCTL_CMD_MOTWR:
100 case DPAUX_DP_AUXCTL_CMD_AUXWR:
101 break;
102 default:
103 printk(BIOS_ERR, "dp: aux write cmd 0x%x is invalid\n",
104 cmd);
105 return -1;
106 }
107
108 tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);
109 for (i = 0; i < DP_AUX_MAX_BYTES / 4; ++i) {
110 memcpy(&temp_data, data, 4);
111 tegra_dpaux_writel(dp, DPAUX_DP_AUXDATA_WRITE_W(i), temp_data);
112 data += 4;
113 }
114
115 reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);
116 reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK;
117 reg_val |= cmd;
118 reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;
119 reg_val |= ((*size - 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
120
121 while ((timeout_retries > 0) && (defer_retries > 0)) {
122 if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
123 (defer_retries != DP_AUX_DEFER_MAX_TRIES))
124 udelay(1);
125
126 reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING;
127 tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
128
129 if (tegra_dpaux_wait_transaction(dp))
130 printk(BIOS_ERR, "dp: aux write transaction timeout\n");
131
132 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
133
134 if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
135 (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
136 (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
137 (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {
138 if (timeout_retries-- > 0) {
139 printk(BIOS_INFO, "dp: aux write retry (0x%x) -- %d\n",
140 *aux_stat, timeout_retries);
141 /* clear the error bits */
142 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, *aux_stat);
143 continue;
144 } else {
145 printk(BIOS_ERR, "dp: aux write got error (0x%x)\n",
146 *aux_stat);
147 return -1;
148 }
149 }
150
151 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||
152 (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
153 if (defer_retries-- > 0) {
154 printk(BIOS_INFO, "dp: aux write defer (0x%x) -- %d\n",
155 *aux_stat, defer_retries);
156 /* clear the error bits */
157 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, *aux_stat);
158 continue;
159 } else {
160 printk(BIOS_ERR, "dp: aux write defer exceeds max retries "
161 "(0x%x)\n", *aux_stat);
162 return -1;
163 }
164 }
165
166 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) ==
167 DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) {
168 *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
169 return 0;
170 } else {
171 printk(BIOS_ERR, "dp: aux write failed (0x%x)\n",
172 *aux_stat);
173 return -1;
174 }
175 }
176 /* Should never come to here */
177 return -1;
178 }
179
180 static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
181 u32 addr, u8 *data, u32 *size,
182 u32 *aux_stat)
183 {
184 u32 reg_val;
185 u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
186 u32 defer_retries = DP_AUX_DEFER_MAX_TRIES;
187
188 if (*size > DP_AUX_MAX_BYTES)
189 return -1; /* only read one chunk */
190
191 /* Check to make sure the command is read command */
192 switch (cmd) {
193 case DPAUX_DP_AUXCTL_CMD_I2CRD:
194 case DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT:
195 case DPAUX_DP_AUXCTL_CMD_MOTRD:
196 case DPAUX_DP_AUXCTL_CMD_AUXRD:
197 break;
198 default:
199 printk(BIOS_ERR, "dp: aux read cmd 0x%x is invalid\n",
200 cmd);
201 return -1;
202 }
203
204 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
205 if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
206 printk(BIOS_SPEW, "dp: HPD is not detected\n");
207 return -1;
208 }
209
210 tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);
211
212 reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);
213 reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK;
214 reg_val |= cmd;
215 reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;
216 reg_val |= ((*size - 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
217 while ((timeout_retries > 0) && (defer_retries > 0)) {
218 if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
219 (defer_retries != DP_AUX_DEFER_MAX_TRIES))
220 udelay(DP_DPCP_RETRY_SLEEP_NS * 2);
221
222 reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING;
223 tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
224
225 if (tegra_dpaux_wait_transaction(dp))
226 printk(BIOS_INFO, "dp: aux read transaction timeout\n");
227
228 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
229
230 if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
231 (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
232 (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
233 (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {
234 if (timeout_retries-- > 0) {
235 printk(BIOS_INFO, "dp: aux read retry (0x%x)"
236 " -- %d\n", *aux_stat,
237 timeout_retries);
238 /* clear the error bits */
239 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
240 *aux_stat);
241 continue; /* retry */
242 } else {
243 printk(BIOS_ERR, "dp: aux read got error"
244 " (0x%x)\n", *aux_stat);
245 return -1;
246 }
247 }
248
249 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||
250 (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
251 if (defer_retries-- > 0) {
252 printk(BIOS_INFO, "dp: aux read defer (0x%x) -- %d\n",
253 *aux_stat, defer_retries);
254 /* clear the error bits */
255 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, *aux_stat);
256 continue;
257 } else {
258 printk(BIOS_INFO, "dp: aux read defer exceeds max retries "
259 "(0x%x)\n", *aux_stat);
260 return -1;
261 }
262 }
263
264 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) ==
265 DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) {
266 int i;
267 u32 temp_data[4];
268
269 for (i = 0; i < DP_AUX_MAX_BYTES / 4; ++i)
270 temp_data[i] = tegra_dpaux_readl(dp,
271 DPAUX_DP_AUXDATA_READ_W(i));
272
273 *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
274 memcpy(data, temp_data, *size);
275
276 return 0;
277 } else {
278 printk(BIOS_ERR, "dp: aux read failed (0x%x\n",
279 *aux_stat);
280 return -1;
281 }
282 }
283 /* Should never come to here */
284 printk(BIOS_ERR, "%s: can't\n", __func__);
285 return -1;
286 }
287
288 static int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
289 u8 *data, u32 *size, u32 *aux_stat)
290 {
291 u32 finished = 0;
292 u32 cur_size;
293 int ret = 0;
294
295 do {
296 cur_size = *size - finished;
297 if (cur_size > DP_AUX_MAX_BYTES)
298 cur_size = DP_AUX_MAX_BYTES;
299
300 ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr,
301 data, &cur_size, aux_stat);
302 if (ret)
303 break;
304
305 /* cur_size should be the real size returned */
306 addr += cur_size;
307 data += cur_size;
308 finished += cur_size;
309
310 } while (*size > finished);
311
312 *size = finished;
313 return ret;
314 }
315
316 static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd,
317 u8 *data_ptr)
318 {
319 u32 size = 1;
320 u32 status = 0;
321 int ret;
322
323 ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
324 cmd, data_ptr, &size, &status);
325 if (ret)
326 printk(BIOS_ERR,
327 "dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n",
328 cmd, status);
329
330 return ret;
331 }
332
333 static int tegra_dc_dp_dpcd_write(struct tegra_dc_dp_data *dp, u32 cmd,
334 u8 data)
335 {
336 u32 size = 1;
337 u32 status = 0;
338 int ret;
339
340 ret = tegra_dc_dpaux_write_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXWR,
341 cmd, &data, &size, &status);
342 if (ret)
343 printk(BIOS_ERR,
344 "dp: Failed to write DPCD data. CMD 0x%x, Status 0x%x\n",
345 cmd, status);
346 return ret;
347 }
348
349 static int tegra_dc_i2c_aux_read(struct tegra_dc_dp_data *dp, u32 i2c_addr,
350 u8 addr, u8 *data, u32 *size, u32 *aux_stat)
351 {
352 u32 finished = 0;
353 int ret = 0;
354
355 do {
356 u32 cur_size = MIN(DP_AUX_MAX_BYTES, *size - finished);
357
358 u32 len = 1;
359 ret = tegra_dc_dpaux_write_chunk(
360 dp, DPAUX_DP_AUXCTL_CMD_MOTWR, i2c_addr,
361 &addr, &len, aux_stat);
362 if (ret) {
363 printk(BIOS_ERR, "%s: error sending address to read.\n",
364 __func__);
365 break;
366 }
367
368 ret = tegra_dc_dpaux_read_chunk(
369 dp, DPAUX_DP_AUXCTL_CMD_I2CRD, i2c_addr,
370 data, &cur_size, aux_stat);
371 if (ret) {
372 printk(BIOS_ERR, "%s: error reading data.\n", __func__);
373 break;
374 }
375
376 /* cur_size should be the real size returned */
377 addr += cur_size;
378 data += cur_size;
379 finished += cur_size;
380 } while (*size > finished);
381
382 *size = finished;
383 return ret;
384 }
385
386 static void tegra_dc_dpaux_enable(struct tegra_dc_dp_data *dp)
387 {
388 /* clear interrupt */
389 tegra_dpaux_writel(dp, DPAUX_INTR_AUX, 0xffffffff);
390 /* do not enable interrupt for now. Enable them when Isr in place */
391 tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, 0x0);
392
393 tegra_dpaux_writel(dp, DPAUX_HYBRID_PADCTL,
394 DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 |
395 DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 |
396 0x18 << DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT |
397 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE);
398
399 tegra_dpaux_writel(dp, DPAUX_HYBRID_SPARE,
400 DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP);
401 }
402
403 static void tegra_dc_dp_dump_link_cfg(struct tegra_dc_dp_data *dp,
404 const struct tegra_dc_dp_link_config *link_cfg)
405 {
406 printk(BIOS_INFO, "DP config: cfg_name "
407 "cfg_value\n");
408 printk(BIOS_INFO, " Lane Count %d\n",
409 link_cfg->max_lane_count);
410 printk(BIOS_INFO, " SupportEnhancedFraming %s\n",
411 link_cfg->support_enhanced_framing ? "Y" : "N");
412 printk(BIOS_INFO, " Bandwidth %d\n",
413 link_cfg->max_link_bw);
414 printk(BIOS_INFO, " bpp %d\n",
415 link_cfg->bits_per_pixel);
416 printk(BIOS_INFO, " EnhancedFraming %s\n",
417 link_cfg->enhanced_framing ? "Y" : "N");
418 printk(BIOS_INFO, " Scramble_enabled %s\n",
419 link_cfg->scramble_ena ? "Y" : "N");
420 printk(BIOS_INFO, " LinkBW %d\n",
421 link_cfg->link_bw);
422 printk(BIOS_INFO, " lane_count %d\n",
423 link_cfg->lane_count);
424 printk(BIOS_INFO, " activespolarity %d\n",
425 link_cfg->activepolarity);
426 printk(BIOS_INFO, " active_count %d\n",
427 link_cfg->active_count);
428 printk(BIOS_INFO, " tu_size %d\n",
429 link_cfg->tu_size);
430 printk(BIOS_INFO, " active_frac %d\n",
431 link_cfg->active_frac);
432 printk(BIOS_INFO, " watermark %d\n",
433 link_cfg->watermark);
434 printk(BIOS_INFO, " hblank_sym %d\n",
435 link_cfg->hblank_sym);
436 printk(BIOS_INFO, " vblank_sym %d\n",
437 link_cfg->vblank_sym);
438 }
439
440 static int _tegra_dp_lower_link_config(struct tegra_dc_dp_data *dp,
441 struct tegra_dc_dp_link_config *cfg)
442 {
443 switch (cfg->link_bw){
444 case SOR_LINK_SPEED_G1_62:
445 if (cfg->max_link_bw > SOR_LINK_SPEED_G1_62)
446 cfg->link_bw = SOR_LINK_SPEED_G2_7;
447 cfg->lane_count /= 2;
448 break;
449 case SOR_LINK_SPEED_G2_7:
450 cfg->link_bw = SOR_LINK_SPEED_G1_62;
451 break;
452 case SOR_LINK_SPEED_G5_4:
453 if (cfg->lane_count == 1) {
454 cfg->link_bw = SOR_LINK_SPEED_G2_7;
455 cfg->lane_count = cfg->max_lane_count;
456 } else
457 cfg->lane_count /= 2;
458 break;
459 default:
460 printk(BIOS_ERR,"dp: Error link rate %d\n", cfg->link_bw);
461 return DP_LT_FAILED;
462 }
463
464 return (cfg->lane_count > 0) ? DP_LT_SUCCESS : DP_LT_FAILED;
465 }
466
467 /* Calculate if given cfg can meet the mode request. */
468 /* Return true if mode is possible, false otherwise. */
469 static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
470 const struct soc_nvidia_tegra124_config *config,
471 struct tegra_dc_dp_link_config *link_cfg)
472 {
473 const u32 link_rate = 27 * link_cfg->link_bw * 1000 * 1000;
474 const u64 f = 100000; /* precision factor */
475
476 u32 num_linkclk_line; /* Number of link clocks per line */
477 u64 ratio_f; /* Ratio of incoming to outgoing data rate */
478
479 u64 frac_f;
480 u64 activesym_f; /* Activesym per TU */
481 u64 activecount_f;
482 u32 activecount;
483 u32 activepolarity;
484 u64 approx_value_f;
485 u32 activefrac = 0;
486 u64 accumulated_error_f = 0;
487 u32 lowest_neg_activecount = 0;
488 u32 lowest_neg_activepolarity = 0;
489 u32 lowest_neg_tusize = 64;
490 u32 num_symbols_per_line;
491 u64 lowest_neg_activefrac = 0;
492 u64 lowest_neg_error_f = 64 * f;
493 u64 watermark_f;
494
495 int i;
496 int neg;
497
498 if (!link_rate || !link_cfg->lane_count || !config->pixel_clock ||
499 !link_cfg->bits_per_pixel)
500 return -1;
501
502 if ((u64)config->pixel_clock * link_cfg->bits_per_pixel >=
503 (u64)link_rate * 8 * link_cfg->lane_count)
504 return -1;
505
506 num_linkclk_line = (u32)((u64)link_rate * (u64)config->xres / config->pixel_clock);
507
508 ratio_f = (u64)config->pixel_clock * link_cfg->bits_per_pixel * f;
509 ratio_f /= 8;
510 ratio_f = (u64)(ratio_f / (link_rate * link_cfg->lane_count));
511
512 for (i = 64; i >= 32; --i) {
513 activesym_f = ratio_f * i;
514 activecount_f = (u64)(activesym_f / (u32)f) * f;
515 frac_f = activesym_f - activecount_f;
516 activecount = (u32)((u64)(activecount_f / (u32)f));
517
518 if (frac_f < (f / 2)) /* fraction < 0.5 */
519 activepolarity = 0;
520 else {
521 activepolarity = 1;
522 frac_f = f - frac_f;
523 }
524
525 if (frac_f != 0) {
526 frac_f = (u64)((f * f) / frac_f); /* 1/fraction */
527 if (frac_f > (15 * f))
528 activefrac = activepolarity ? 1 : 15;
529 else
530 activefrac = activepolarity ?
531 (u32)((u64)(frac_f / (u32)f)) + 1 :
532 (u32)((u64)(frac_f / (u32)f));
533 }
534
535 if (activefrac == 1)
536 activepolarity = 0;
537
538 if (activepolarity == 1)
539 approx_value_f = activefrac ? (u64)(
540 (activecount_f + (activefrac * f - f) * f) /
541 (activefrac * f)) :
542 activecount_f + f;
543 else
544 approx_value_f = activefrac ?
545 activecount_f + (u64)(f / activefrac) :
546 activecount_f;
547
548 if (activesym_f < approx_value_f) {
549 accumulated_error_f = num_linkclk_line *
550 (u64)((approx_value_f - activesym_f) / i);
551 neg = 1;
552 } else {
553 accumulated_error_f = num_linkclk_line *
554 (u64)((activesym_f - approx_value_f) / i);
555 neg = 0;
556 }
557
558 if ((neg && (lowest_neg_error_f > accumulated_error_f)) ||
559 (accumulated_error_f == 0)) {
560 lowest_neg_error_f = accumulated_error_f;
561 lowest_neg_tusize = i;
562 lowest_neg_activecount = activecount;
563 lowest_neg_activepolarity = activepolarity;
564 lowest_neg_activefrac = activefrac;
565
566 if (accumulated_error_f == 0)
567 break;
568 }
569 }
570
571 if (lowest_neg_activefrac == 0) {
572 link_cfg->activepolarity = 0;
573 link_cfg->active_count = lowest_neg_activepolarity ?
574 lowest_neg_activecount : lowest_neg_activecount - 1;
575 link_cfg->tu_size = lowest_neg_tusize;
576 link_cfg->active_frac = 1;
577 } else {
578 link_cfg->activepolarity = lowest_neg_activepolarity;
579 link_cfg->active_count = (u32)lowest_neg_activecount;
580 link_cfg->tu_size = lowest_neg_tusize;
581 link_cfg->active_frac = (u32)lowest_neg_activefrac;
582 }
583
584 watermark_f = (u64)((ratio_f * link_cfg->tu_size * (f - ratio_f)) / f);
585 link_cfg->watermark = (u32)((u64)((watermark_f + lowest_neg_error_f) /
586 f)) + link_cfg->bits_per_pixel / 4 - 1;
587 num_symbols_per_line = (config->xres * link_cfg->bits_per_pixel) /
588 (8 * link_cfg->lane_count);
589
590 if (link_cfg->watermark > 30) {
591 printk(BIOS_INFO,
592 "dp: sor setting: unable to get a good tusize, "
593 "force watermark to 30.\n");
594 link_cfg->watermark = 30;
595 return -1;
596 } else if (link_cfg->watermark > num_symbols_per_line) {
597 printk(BIOS_INFO,
598 "dp: sor setting: force watermark to the number "
599 "of symbols in the line.\n");
600 link_cfg->watermark = num_symbols_per_line;
601 return -1;
602 }
603
604 /* Refer to dev_disp.ref for more information. */
605 /* # symbols/hblank = ((SetRasterBlankEnd.X + SetRasterSize.Width - */
606 /* SetRasterBlankStart.X - 7) * link_clk / pclk) */
607 /* - 3 * enhanced_framing - Y */
608 /* where Y = (# lanes == 4) 3 : (# lanes == 2) ? 6 : 12 */
609 link_cfg->hblank_sym = (int)((u64)(((u64)(config->hback_porch +
610 config->hfront_porch + config->hsync_width - 7) *
611 link_rate) / config->pixel_clock)) -
612 3 * link_cfg->enhanced_framing -
613 (12 / link_cfg->lane_count);
614
615 if (link_cfg->hblank_sym < 0)
616 link_cfg->hblank_sym = 0;
617
618 /* Refer to dev_disp.ref for more information. */
619 /* # symbols/vblank = ((SetRasterBlankStart.X - */
620 /* SetRasterBlankEen.X - 25) * link_clk / pclk) */
621 /* - Y - 1; */
622 /* where Y = (# lanes == 4) 12 : (# lanes == 2) ? 21 : 39 */
623 link_cfg->vblank_sym = (int)((u64)((u64)(config->xres - 25)
624 * link_rate / config->pixel_clock)) - (36 /
625 link_cfg->lane_count) - 4;
626
627 if (link_cfg->vblank_sym < 0)
628 link_cfg->vblank_sym = 0;
629
630 link_cfg->is_valid = 1;
631 tegra_dc_dp_dump_link_cfg(dp, link_cfg);
632
633 return 0;
634 }
635
636 static int tegra_dc_dp_init_max_link_cfg(
637 struct soc_nvidia_tegra124_config *config,
638 struct tegra_dc_dp_data *dp,
639 struct tegra_dc_dp_link_config *link_cfg)
640 {
641 u8 dpcd_data;
642 int ret;
643
644 CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LANE_COUNT,
645 &dpcd_data));
646 link_cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK;
647 link_cfg->tps3_supported = (dpcd_data &
648 NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES) ? 1 : 0;
649
650 link_cfg->support_enhanced_framing =
651 (dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ?
652 1 : 0;
653
654 CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_DOWNSPREAD,
655 &dpcd_data));
656 link_cfg->downspread = (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT)?
657 1 : 0;
658
659 CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_TRAINING_AUX_RD_INTERVAL,
660 &link_cfg->aux_rd_interval));
661
662 CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LINK_BANDWIDTH,
663 &link_cfg->max_link_bw));
664
665 link_cfg->bits_per_pixel = config->panel_bits_per_pixel;
666
667 /*
668 * Set to a high value for link training and attach.
669 * Will be re-programmed when dp is enabled.
670 */
671 link_cfg->drive_current = config->drive_current;
672 link_cfg->preemphasis = config->preemphasis;
673 link_cfg->postcursor = config->postcursor;
674
675 CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP,
676 &dpcd_data));
677 link_cfg->alt_scramber_reset_cap =
678 (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ?
679 1 : 0;
680 link_cfg->only_enhanced_framing =
681 (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ?
682 1 : 0;
683
684 link_cfg->lane_count = link_cfg->max_lane_count;
685 link_cfg->link_bw = link_cfg->max_link_bw;
686 link_cfg->enhanced_framing = link_cfg->support_enhanced_framing;
687
688 tegra_dc_dp_calc_config(dp, config, link_cfg);
689 return 0;
690 }
691
692 static int tegra_dc_dp_set_assr(struct tegra_dc_dp_data *dp, int ena)
693 {
694 int ret;
695
696 u8 dpcd_data = ena ?
697 NV_DPCD_EDP_CONFIG_SET_ASC_RESET_ENABLE :
698 NV_DPCD_EDP_CONFIG_SET_ASC_RESET_DISABLE;
699
700 CHECK_RET(tegra_dc_dp_dpcd_write(dp, NV_DPCD_EDP_CONFIG_SET,
701 dpcd_data));
702
703 /* Also reset the scrambler to 0xfffe */
704 tegra_dc_sor_set_internal_panel(&dp->sor, ena);
705 return 0;
706 }
707
708 static int tegra_dp_set_link_bandwidth(struct tegra_dc_dp_data *dp, u8 link_bw)
709 {
710 tegra_dc_sor_set_link_bandwidth(&dp->sor, link_bw);
711
712 /* Sink side */
713 return tegra_dc_dp_dpcd_write(dp, NV_DPCD_LINK_BANDWIDTH_SET, link_bw);
714 }
715
716 static int tegra_dp_set_lane_count(struct tegra_dc_dp_data *dp,
717 const struct tegra_dc_dp_link_config *link_cfg)
718 {
719 u8 dpcd_data;
720 int ret;
721
722 /* check if panel support enhanched_framing */
723 dpcd_data = link_cfg->lane_count;
724 if (link_cfg->enhanced_framing)
725 dpcd_data |= NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T;
726 CHECK_RET(tegra_dc_dp_dpcd_write(dp, NV_DPCD_LANE_COUNT_SET,
727 dpcd_data));
728
729 tegra_dc_sor_set_lane_count(&dp->sor, link_cfg->lane_count);
730
731 /* Also power down lanes that will not be used */
732 return 0;
733 }
734
735 static int tegra_dc_dp_link_trained(struct tegra_dc_dp_data *dp,
736 const struct tegra_dc_dp_link_config *cfg)
737 {
738 u32 lane;
739 u8 mask;
740 u8 data;
741 int ret;
742
743 for (lane = 0; lane < cfg->lane_count; ++lane) {
744 CHECK_RET(tegra_dc_dp_dpcd_read(dp, (lane/2) ?
745 NV_DPCD_LANE2_3_STATUS : NV_DPCD_LANE0_1_STATUS,
746 &data));
747 mask = (lane & 1) ?
748 NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES |
749 NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES |
750 NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES :
751 NV_DPCD_STATUS_LANEX_CR_DONE_YES |
752 NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES |
753 NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES;
754 if ((data & mask) != mask)
755 return -1;
756 }
757 return 0;
758 }
759
760 static int tegra_dp_channel_eq_status(struct tegra_dc_dp_data *dp)
761 {
762 u32 cnt;
763 u32 n_lanes = dp->link_cfg.lane_count;
764 u8 data;
765 u8 ce_done = 1;
766
767 for (cnt = 0; cnt < n_lanes / 2; cnt++) {
768 tegra_dc_dp_dpcd_read(dp, (NV_DPCD_LANE0_1_STATUS + cnt), &data);
769
770 if (n_lanes == 1) {
771 ce_done = (data &
772 (0x1 << NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT)) &&
773 (data & (0x1 << NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT));
774 break;
775 } else if (!(data & (0x1 << NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT)) ||
776 !(data & (0x1 << NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT)) ||
777 !(data & (0x1 << NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT)) ||
778 !(data & (0x1 << NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT)))
779 return 0;
780 }
781
782 if (ce_done) {
783 tegra_dc_dp_dpcd_read(dp, NV_DPCD_LANE_ALIGN_STATUS_UPDATED, &data);
784 if (!(data & NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES))
785 ce_done = 0;
786 }
787
788 return ce_done;
789 }
790
791 static u8 tegra_dp_clock_recovery_status(struct tegra_dc_dp_data *dp)
792 {
793 u32 cnt;
794 u32 n_lanes = dp->link_cfg.lane_count;
795 u8 data_ptr;
796
797 for (cnt = 0; cnt < n_lanes / 2; cnt++) {
798 tegra_dc_dp_dpcd_read(dp,
799 (NV_DPCD_LANE0_1_STATUS + cnt), &data_ptr);
800
801 if (n_lanes == 1)
802 return (data_ptr & NV_DPCD_STATUS_LANEX_CR_DONE_YES) ? 1 : 0;
803 else if (!(data_ptr & NV_DPCD_STATUS_LANEX_CR_DONE_YES) ||
804 !(data_ptr &
805 (NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES)))
806 return 0;
807 }
808
809 return 1;
810 }
811
812 static void tegra_dp_lt_adjust(struct tegra_dc_dp_data *dp,
813 u32 pe[4], u32 vs[4], u32 pc[4],
814 u8 pc_supported)
815 {
816 size_t cnt;
817 u8 data_ptr;
818 u32 n_lanes = dp->link_cfg.lane_count;
819
820 for (cnt = 0; cnt < n_lanes / 2; cnt++) {
821 tegra_dc_dp_dpcd_read(dp,
822 (NV_DPCD_LANE0_1_ADJUST_REQ + cnt), &data_ptr);
823 pe[2 * cnt] = (data_ptr & NV_DPCD_ADJUST_REQ_LANEX_PE_MASK) >>
824 NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT;
825 vs[2 * cnt] = (data_ptr & NV_DPCD_ADJUST_REQ_LANEX_DC_MASK) >>
826 NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT;
827 pe[1 + 2 * cnt] =
828 (data_ptr & NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK) >>
829 NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT;
830 vs[1 + 2 * cnt] =
831 (data_ptr & NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK) >>
832 NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT;
833 }
834 if (pc_supported) {
835 tegra_dc_dp_dpcd_read(dp,
836 NV_DPCD_ADJUST_REQ_POST_CURSOR2, &data_ptr);
837 for (cnt = 0; cnt < n_lanes; cnt++) {
838 pc[cnt] = (data_ptr >>
839 NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(cnt)) &
840 NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK;
841 }
842 }
843 }
844
845 static inline u32 tegra_dp_wait_aux_training(struct tegra_dc_dp_data *dp,
846 u8 is_clk_recovery)
847 {
848 if (!dp->link_cfg.aux_rd_interval)
849 is_clk_recovery ? udelay(200) :
850 udelay(500);
851 else
852 mdelay(dp->link_cfg.aux_rd_interval * 4);
853
854 return dp->link_cfg.aux_rd_interval;
855 }
856
857 static void tegra_dp_tpg(struct tegra_dc_dp_data *dp, u32 tp, u32 n_lanes)
858 {
859 u8 data = (tp == training_pattern_disabled)
860 ? (tp | NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F)
861 : (tp | NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T);
862
863 tegra_dc_sor_set_dp_linkctl(&dp->sor, 1, tp, &dp->link_cfg);
864 tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET, data);
865 }
866
867 static int tegra_dp_link_config(struct tegra_dc_dp_data *dp,
868 const struct tegra_dc_dp_link_config *link_cfg)
869 {
870 u8 dpcd_data;
871 u32 retry;
872
873 if (link_cfg->lane_count == 0) {
874 printk(BIOS_ERR, "dp: error: lane count is 0. "
875 "Can not set link config.\n");
876 return DP_LT_FAILED;
877 }
878
879 /* Set power state if it is not in normal level */
880 if (tegra_dc_dp_dpcd_read(dp, NV_DPCD_SET_POWER, &dpcd_data))
881 return DP_LT_FAILED;
882
883 if (dpcd_data == NV_DPCD_SET_POWER_VAL_D3_PWRDWN) {
884 dpcd_data = NV_DPCD_SET_POWER_VAL_D0_NORMAL;
885
886 /* DP spec requires 3 retries */
887 for (retry = 3; retry > 0; --retry){
888 if (tegra_dc_dp_dpcd_write(dp, NV_DPCD_SET_POWER, dpcd_data))
889 break;
890 if (retry == 1){
891 printk(BIOS_ERR, "dp: Failed to set DP panel power\n");
892 return DP_LT_FAILED;
893 }
894 }
895 }
896
897 /* Enable ASSR if possible */
898 if (link_cfg->alt_scramber_reset_cap)
899 if (tegra_dc_dp_set_assr(dp, 1))
900 return DP_LT_FAILED;
901
902 if (tegra_dp_set_link_bandwidth(dp, link_cfg->link_bw)) {
903 printk(BIOS_ERR, "dp: Failed to set link bandwidth\n");
904 return DP_LT_FAILED;
905 }
906 if (tegra_dp_set_lane_count(dp, link_cfg)) {
907 printk(BIOS_ERR, "dp: Failed to set lane count\n");
908 return DP_LT_FAILED;
909 }
910 tegra_dc_sor_set_dp_linkctl(&dp->sor, 1, training_pattern_none,
911 link_cfg);
912 return DP_LT_SUCCESS;
913 }
914
915 static int tegra_dp_lower_link_config(struct tegra_dc_dp_data *dp,
916 struct tegra_dc_dp_link_config *cfg)
917 {
918 struct tegra_dc_dp_link_config tmp_cfg;
919
920 tmp_cfg = dp->link_cfg;
921 cfg->is_valid = 0;
922
923 if (_tegra_dp_lower_link_config(dp, cfg))
924 goto fail;
925
926 if (tegra_dc_dp_calc_config(dp, dp->dc->config, cfg))
927 goto fail;
928 tegra_dp_link_config(dp, cfg);
929
930 return DP_LT_SUCCESS;
931 fail:
932 dp->link_cfg = tmp_cfg;
933 tegra_dp_link_config(dp, &tmp_cfg);
934 return DP_LT_FAILED;
935 }
936
937 static void tegra_dp_lt_config(struct tegra_dc_dp_data *dp,
938 u32 pe[4], u32 vs[4], u32 pc[4])
939 {
940 struct tegra_dc_sor_data *sor = &dp->sor;
941 u32 n_lanes = dp->link_cfg.lane_count;
942 u8 pc_supported = dp->link_cfg.tps3_supported;
943 u32 cnt;
944 u32 val;
945
946 for (cnt = 0; cnt < n_lanes; cnt++) {
947 u32 mask = 0;
948 u32 pe_reg, vs_reg, pc_reg;
949 u32 shift = 0;
950
951 switch (cnt) {
952 case 0:
953 mask = NV_SOR_PR_LANE2_DP_LANE0_MASK;
954 shift = NV_SOR_PR_LANE2_DP_LANE0_SHIFT;
955 break;
956 case 1:
957 mask = NV_SOR_PR_LANE1_DP_LANE1_MASK;
958 shift = NV_SOR_PR_LANE1_DP_LANE1_SHIFT;
959 break;
960 case 2:
961 mask = NV_SOR_PR_LANE0_DP_LANE2_MASK;
962 shift = NV_SOR_PR_LANE0_DP_LANE2_SHIFT;
963 break;
964 case 3:
965 mask = NV_SOR_PR_LANE3_DP_LANE3_MASK;
966 shift = NV_SOR_PR_LANE3_DP_LANE3_SHIFT;
967 break;
968 default:
969 printk(BIOS_ERR,
970 "dp: incorrect lane cnt\n");
971 }
972
973 pe_reg = tegra_dp_pe_regs[pc[cnt]][vs[cnt]][pe[cnt]];
974 vs_reg = tegra_dp_vs_regs[pc[cnt]][vs[cnt]][pe[cnt]];
975 pc_reg = tegra_dp_pc_regs[pc[cnt]][vs[cnt]][pe[cnt]];
976
977 tegra_dp_set_pe_vs_pc(sor, mask, pe_reg << shift,
978 vs_reg << shift, pc_reg << shift, pc_supported);
979 }
980
981 tegra_dp_disable_tx_pu(&dp->sor);
982 udelay(20);
983
984 for (cnt = 0; cnt < n_lanes; cnt++) {
985 u32 max_vs_flag = tegra_dp_is_max_vs(pe[cnt], vs[cnt]);
986 u32 max_pe_flag = tegra_dp_is_max_pe(pe[cnt], vs[cnt]);
987
988 val = (vs[cnt] << NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT) |
989 (max_vs_flag ?
990 NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T :
991 NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F) |
992 (pe[cnt] << NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT) |
993 (max_pe_flag ?
994 NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T :
995 NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F);
996 tegra_dc_dp_dpcd_write(dp,
997 (NV_DPCD_TRAINING_LANE0_SET + cnt), val);
998 }
999
1000 if (pc_supported) {
1001 for (cnt = 0; cnt < n_lanes / 2; cnt++) {
1002 u32 max_pc_flag0 = tegra_dp_is_max_pc(pc[cnt]);
1003 u32 max_pc_flag1 = tegra_dp_is_max_pc(pc[cnt + 1]);
1004 val = (pc[cnt] << NV_DPCD_LANEX_SET2_PC2_SHIFT) |
1005 (max_pc_flag0 ?
1006 NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T :
1007 NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_F) |
1008 (pc[cnt + 1] <<
1009 NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT) |
1010 (max_pc_flag1 ?
1011 NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T :
1012 NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F);
1013 tegra_dc_dp_dpcd_write(dp,
1014 (NV_DPCD_TRAINING_LANE0_1_SET2 + cnt), val);
1015 }
1016 }
1017 }
1018
1019 static int _tegra_dp_channel_eq(struct tegra_dc_dp_data *dp, u32 pe[4],
1020 u32 vs[4], u32 pc[4], u8 pc_supported,
1021 u32 n_lanes)
1022 {
1023 u32 retry_cnt;
1024
1025 for (retry_cnt = 0; retry_cnt < 4; retry_cnt++) {
1026 if (retry_cnt){
1027 tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported);
1028 tegra_dp_lt_config(dp, pe, vs, pc);
1029 }
1030
1031 tegra_dp_wait_aux_training(dp, 0);
1032
1033 if (!tegra_dp_clock_recovery_status(dp)) {
1034 printk(BIOS_ERR,"dp: CR failed in channel EQ sequence!\n");
1035 break;
1036 }
1037
1038 if (tegra_dp_channel_eq_status(dp))
1039 return DP_LT_SUCCESS;
1040 }
1041
1042 return DP_LT_FAILED;
1043 }
1044
1045 static int tegra_dp_channel_eq(struct tegra_dc_dp_data *dp,
1046 u32 pe[4], u32 vs[4], u32 pc[4])
1047 {
1048 u32 n_lanes = dp->link_cfg.lane_count;
1049 u8 pc_supported = dp->link_cfg.tps3_supported;
1050 int err;
1051 u32 tp_src = training_pattern_2;
1052
1053 if (pc_supported)
1054 tp_src = training_pattern_3;
1055
1056 tegra_dp_tpg(dp, tp_src, n_lanes);
1057
1058 err = _tegra_dp_channel_eq(dp, pe, vs, pc, pc_supported, n_lanes);
1059
1060 tegra_dp_tpg(dp, training_pattern_disabled, n_lanes);
1061
1062 return err;
1063 }
1064
1065 static int _tegra_dp_clk_recovery(struct tegra_dc_dp_data *dp, u32 pe[4],
1066 u32 vs[4], u32 pc[4], u8 pc_supported,
1067 u32 n_lanes)
1068 {
1069 u32 vs_temp[4];
1070 u32 retry_cnt = 0;
1071
1072 do {
1073 tegra_dp_lt_config(dp, pe, vs, pc);
1074 tegra_dp_wait_aux_training(dp, 1);
1075
1076 if (tegra_dp_clock_recovery_status(dp))
1077 return DP_LT_SUCCESS;
1078
1079 memcpy(vs_temp, vs, sizeof(vs_temp));
1080 tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported);
1081
1082 if (memcmp(vs_temp, vs, sizeof(vs_temp)))
1083 retry_cnt = 0;
1084 else
1085 ++retry_cnt;
1086 } while (retry_cnt < 5);
1087
1088 return DP_LT_FAILED;
1089 }
1090
1091 static int tegra_dp_clk_recovery(struct tegra_dc_dp_data *dp,
1092 u32 pe[4], u32 vs[4], u32 pc[4])
1093 {
1094 u32 n_lanes = dp->link_cfg.lane_count;
1095 u8 pc_supported = dp->link_cfg.tps3_supported;
1096 int err;
1097
1098 tegra_dp_tpg(dp, training_pattern_1, n_lanes);
1099
1100 err = _tegra_dp_clk_recovery(dp, pe, vs, pc, pc_supported, n_lanes);
1101 if (err < 0)
1102 tegra_dp_tpg(dp, training_pattern_disabled, n_lanes);
1103
1104 return err;
1105 }
1106
1107 static int tegra_dc_dp_full_link_training(struct tegra_dc_dp_data *dp)
1108 {
1109 struct tegra_dc_sor_data *sor = &dp->sor;
1110 int err;
1111 u32 pe[4], vs[4], pc[4];
1112
1113 tegra_sor_precharge_lanes(sor);
1114
1115 retry_cr:
1116 memset(pe, preEmphasis_Disabled, sizeof(pe));
1117 memset(vs, driveCurrent_Level0, sizeof(vs));
1118 memset(pc, postCursor2_Level0, sizeof(pc));
1119
1120 err = tegra_dp_clk_recovery(dp, pe, vs, pc);
1121 if (err != DP_LT_SUCCESS) {
1122 if (!tegra_dp_lower_link_config(dp, &dp->link_cfg))
1123 goto retry_cr;
1124
1125 printk(BIOS_ERR, "dp: clk recovery failed\n");
1126 goto fail;
1127 }
1128
1129 err = tegra_dp_channel_eq(dp, pe, vs, pc);
1130 if (err != DP_LT_SUCCESS) {
1131 if (!tegra_dp_lower_link_config(dp, &dp->link_cfg))
1132 goto retry_cr;
1133
1134 printk(BIOS_ERR,
1135 "dp: channel equalization failed\n");
1136 goto fail;
1137 }
1138
1139 tegra_dc_dp_dump_link_cfg(dp, &dp->link_cfg);
1140
1141 return 0;
1142
1143 fail:
1144 return err;
1145 }
1146 /*
1147 * All link training functions are ported from kernel dc driver.
1148 * See more details at drivers/video/tegra/dc/dp.c
1149 */
1150 static int tegra_dc_dp_fast_link_training(struct tegra_dc_dp_data *dp,
1151 const struct tegra_dc_dp_link_config *link_cfg)
1152 {
1153 struct tegra_dc_sor_data *sor = &dp->sor;
1154 u8 link_bw;
1155 u8 lane_count;
1156 u16 data16;
1157 u32 data32;
1158 u32 size;
1159 u32 status;
1160 int j;
1161 u32 mask = 0xffff >> ((4 - link_cfg->lane_count) * 4);
1162
1163 tegra_dc_sor_set_lane_parm(sor, link_cfg);
1164 tegra_dc_dp_dpcd_write(dp, NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET,
1165 NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B10B);
1166
1167 /* Send TP1 */
1168 tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_1, link_cfg);
1169 tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET,
1170 NV_DPCD_TRAINING_PATTERN_SET_TPS_TP1);
1171
1172 for (j = 0; j < link_cfg->lane_count; ++j)
1173 tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_LANE0_SET + j,
1174 0x24);
1175 udelay(520);
1176
1177 size = sizeof(data16);
1178 tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
1179 NV_DPCD_LANE0_1_STATUS, (u8 *)&data16, &size, &status);
1180 status = mask & 0x1111;
1181 if ((data16 & status) != status) {
1182 printk(BIOS_ERR,
1183 "dp: Link training error for TP1 (%#x)\n", data16);
1184 return -EFAULT;
1185 }
1186
1187 /* enable ASSR */
1188 tegra_dc_dp_set_assr(dp, link_cfg->scramble_ena);
1189 tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_3, link_cfg);
1190
1191 tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET,
1192 link_cfg->link_bw == 20 ? 0x23 : 0x22);
1193 for (j = 0; j < link_cfg->lane_count; ++j)
1194 tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_LANE0_SET + j,
1195 0x24);
1196 udelay(520);
1197
1198 size = sizeof(data32);
1199 tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
1200 NV_DPCD_LANE0_1_STATUS, (u8 *)&data32, &size, &status);
1201 if ((data32 & mask) != (0x7777 & mask)) {
1202 printk(BIOS_ERR,
1203 "dp: Link training error for TP2/3 (0x%x)\n", data32);
1204 return -EFAULT;
1205 }
1206
1207 tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_disabled,
1208 link_cfg);
1209 tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET, 0);
1210
1211 if (tegra_dc_dp_link_trained(dp, link_cfg)) {
1212 tegra_dc_sor_read_link_config(&dp->sor, &link_bw,
1213 &lane_count);
1214 printk(BIOS_ERR,
1215 "Fast link trainging failed, link bw %d, lane # %d\n",
1216 link_bw, lane_count);
1217 return -EFAULT;
1218 }
1219
1220 printk(BIOS_INFO,
1221 "Fast link trainging succeeded, link bw %d, lane %d\n",
1222 link_cfg->link_bw, link_cfg->lane_count);
1223
1224 return 0;
1225 }
1226
1227 static int tegra_dp_do_link_training(struct tegra_dc_dp_data *dp,
1228 const struct tegra_dc_dp_link_config *link_cfg)
1229 {
1230 u8 link_bw;
1231 u8 lane_count;
1232 int ret;
1233
1234 /* Now do the fast link training for eDP */
1235 ret = tegra_dc_dp_fast_link_training(dp, link_cfg);
1236 if (ret) {
1237 printk(BIOS_ERR, "dp: fast link training failed\n");
1238
1239 /* Try full link training then */
1240 if (tegra_dc_dp_full_link_training(dp)){
1241 printk(BIOS_ERR, "dp: full link training failed\n");
1242 return ret;
1243 }
1244 } else {
1245 /* set to a known-good drive setting if fast link succeeded */
1246 tegra_dc_sor_set_voltage_swing(&dp->sor);
1247 }
1248
1249 /* Everything goes well, double check the link config */
1250 /* TODO: record edc/c2 data for debugging */
1251 tegra_dc_sor_read_link_config(&dp->sor, &link_bw, &lane_count);
1252
1253 if ((link_cfg->link_bw == link_bw) &&
1254 (link_cfg->lane_count == lane_count))
1255 return 0;
1256 else
1257 return -EFAULT;
1258 }
1259
1260 static int tegra_dc_dp_explore_link_cfg(struct tegra_dc_dp_data *dp,
1261 struct tegra_dc_dp_link_config *link_cfg,
1262 const struct soc_nvidia_tegra124_config *config)
1263 {
1264 struct tegra_dc_dp_link_config temp_cfg;
1265
1266 if (!config->pixel_clock || !config->xres || !config->yres) {
1267 printk(BIOS_ERR,
1268 "dp: error mode configuration");
1269 return -EINVAL;
1270 }
1271 if (!link_cfg->max_link_bw || !link_cfg->max_lane_count) {
1272 printk(BIOS_ERR,
1273 "dp: error link configuration");
1274 return -EINVAL;
1275 }
1276
1277 link_cfg->is_valid = 0;
1278
1279 memcpy(&temp_cfg, link_cfg, sizeof(temp_cfg));
1280
1281 temp_cfg.link_bw = temp_cfg.max_link_bw;
1282 temp_cfg.lane_count = temp_cfg.max_lane_count;
1283
1284 /*
1285 * set to max link config
1286 */
1287 if ((!tegra_dc_dp_calc_config(dp, config, &temp_cfg)) &&
1288 (!tegra_dp_link_config(dp, &temp_cfg)) &&
1289 (!tegra_dp_do_link_training(dp, &temp_cfg)))
1290 /* the max link cfg is doable */
1291 memcpy(link_cfg, &temp_cfg, sizeof(temp_cfg));
1292
1293 return link_cfg->is_valid ? 0 : -EFAULT;
1294 }
1295
1296 static void tegra_dp_update_config(struct tegra_dc_dp_data *dp,
1297 struct soc_nvidia_tegra124_config *config)
1298 {
1299 struct edid edid;
1300 u8 buf[128] = {0};
1301 u32 size = sizeof(buf), aux_stat = 0;
1302
1303 tegra_dc_dpaux_enable(dp);
1304 if (tegra_dc_i2c_aux_read(dp, TEGRA_EDID_I2C_ADDRESS, 0, buf, &size,
1305 &aux_stat)) {
1306 printk(BIOS_ERR, "%s: Failed to read EDID. Use defaults.\n",
1307 __func__);
1308 return;
1309 }
1310
1311 if (decode_edid(buf, sizeof(buf), &edid) != EDID_CONFORMANT) {
1312 printk(BIOS_ERR, "%s: Failed to decode EDID. Use defaults.\n",
1313 __func__);
1314 return;
1315 }
1316
1317 config->xres = edid.mode.ha;
1318 config->yres = edid.mode.va;
1319 config->pixel_clock = edid.mode.pixel_clock * 1000;
1320
1321 config->hfront_porch = edid.mode.hso;
1322 config->hsync_width = edid.mode.hspw;
1323 config->hback_porch = edid.mode.hbl - edid.mode.hso - edid.mode.hspw;
1324
1325 config->vfront_porch = edid.mode.vso;
1326 config->vsync_width = edid.mode.vspw;
1327 config->vback_porch = edid.mode.vbl - edid.mode.vso - edid.mode.vspw;
1328
1329 /**
1330 * Note edid->framebuffer_bits_per_pixel is currently hard-coded as 32,
1331 * so we should keep the default value in device config.
1332 *
1333 * EDID v1.3 panels may not have color depth info, so we need to check
1334 * if these values are zero before updating config.
1335 */
1336 if (edid.panel_bits_per_pixel)
1337 config->panel_bits_per_pixel = edid.panel_bits_per_pixel;
1338 if (edid.panel_bits_per_color)
1339 config->color_depth = edid.panel_bits_per_color;
1340 printk(BIOS_SPEW, "%s: configuration updated by EDID.\n", __func__);
1341 }
1342
1343 void dp_init(void *_config)
1344 {
1345 struct soc_nvidia_tegra124_config *config = (void *)_config;
1346 struct tegra_dc *dc = config->dc_data;
1347 struct tegra_dc_dp_data *dp = &dp_data;
1348
1349 // set up links among config, dc, dp and sor
1350 dp->dc = dc;
1351 dc->out = dp;
1352 dp->sor.dc = dc;
1353
1354 dp->sor.power_is_up = 0;
1355 dp->sor.base = (void *)TEGRA_ARM_SOR;
1356 dp->sor.pmc_base = (void *)TEGRA_PMC_BASE;
1357 dp->sor.portnum = 0;
1358 dp->sor.link_cfg = &dp->link_cfg;
1359 dp->aux_base = (void *)TEGRA_ARM_DPAUX;
1360 dp->link_cfg.is_valid = 0;
1361 dp->enabled = 0;
1362
1363 tegra_dp_update_config(dp, config);
1364 }
1365
1366 static void tegra_dp_hpd_config(struct tegra_dc_dp_data *dp,
1367 struct soc_nvidia_tegra124_config *config)
1368 {
1369 u32 val;
1370
1371 val = config->hpd_plug_min_us |
1372 (config->hpd_unplug_min_us <<
1373 DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME_SHIFT);
1374 tegra_dpaux_writel(dp, DPAUX_HPD_CONFIG, val);
1375
1376 tegra_dpaux_writel(dp, DPAUX_HPD_IRQ_CONFIG, config->hpd_irq_min_us);
1377 }
1378
1379 static int tegra_dp_hpd_plug(struct tegra_dc_dp_data *dp, int timeout_ms)
1380 {
1381 u32 val;
1382 u32 timeout = timeout_ms * 1000;
1383 do {
1384 val = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
1385 if (val & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)
1386 return 0;
1387 udelay(100);
1388 timeout -= 100;
1389 } while (timeout > 0);
1390 return -1;
1391 }
1392
1393 void dp_enable(void *_dp)
1394 {
1395 struct tegra_dc_dp_data *dp = _dp;
1396 struct tegra_dc *dc = dp->dc;
1397 struct soc_nvidia_tegra124_config *config = dc->config;
1398
1399 u8 data;
1400 u32 retry;
1401 int ret;
1402
1403 tegra_dc_dpaux_enable(dp);
1404
1405 tegra_dp_hpd_config(dp, config);
1406 if (tegra_dp_hpd_plug(dp, config->vdd_to_hpd_delay_ms) < 0) {
1407 printk(BIOS_ERR, "dp: hpd plug failed\n");
1408 goto error_enable;
1409 }
1410
1411 if (tegra_dc_dp_init_max_link_cfg(config, dp, &dp->link_cfg)) {
1412 printk(BIOS_ERR, "dp: failed to init link configuration\n");
1413 goto error_enable;
1414 }
1415
1416 tegra_dc_sor_enable_dp(&dp->sor);
1417
1418 tegra_dc_sor_set_panel_power(&dp->sor, 1);
1419
1420 /* Write power on to DPCD */
1421 data = NV_DPCD_SET_POWER_VAL_D0_NORMAL;
1422 retry = 0;
1423 do {
1424 ret = tegra_dc_dp_dpcd_write(dp,
1425 NV_DPCD_SET_POWER, data);
1426 } while ((retry++ < DP_POWER_ON_MAX_TRIES) && ret);
1427
1428 if (ret || retry >= DP_POWER_ON_MAX_TRIES) {
1429 printk(BIOS_ERR,
1430 "dp: failed to power on panel (0x%x)\n", ret);
1431 goto error_enable;
1432 }
1433
1434 /* Confirm DP is plugging status */
1435 if (!(tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT) &
1436 DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
1437 printk(BIOS_ERR, "dp: could not detect HPD\n");
1438 goto error_enable;
1439 }
1440
1441 /* Check DP version */
1442 if (tegra_dc_dp_dpcd_read(dp, NV_DPCD_REV, &dp->revision))
1443 printk(BIOS_ERR,
1444 "dp: failed to read the revision number from sink\n");
1445
1446 if (tegra_dc_dp_explore_link_cfg(dp, &dp->link_cfg, config)) {
1447 printk(BIOS_ERR, "dp: error to configure link\n");
1448 goto error_enable;
1449 }
1450
1451 tegra_dc_sor_set_power_state(&dp->sor, 1);
1452 tegra_dc_sor_attach(&dp->sor);
1453
1454 /*
1455 * Power down the unused lanes to save power
1456 * (about hundreds milli-watts, varies from boards).
1457 */
1458 tegra_dc_sor_power_down_unused_lanes(&dp->sor);
1459
1460 dp->enabled = 1;
1461 error_enable:
1462 return;
1463 }
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