?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
soc/mediatek/mt8196: Add MT6685 Clock IC driver
[coreboot2.git] / src / soc / nvidia / tegra124 / sor.c
blob2feea6b1c1ca065b107c7bf2ebe2f1929aa728fd
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 /*
4 * drivers/video/tegra/dc/sor.c
5 */
6
7 #include <boot/tables.h>
8 #include <console/console.h>
9 #include <delay.h>
10 #include <device/device.h>
11 #include <soc/addressmap.h>
12 #include <soc/clk_rst.h>
13 #include <soc/clock.h>
14 #include <soc/display.h>
15 #include <soc/nvidia/tegra/dc.h>
16 #include <soc/nvidia/tegra/displayport.h>
17 #include <soc/sor.h>
18 #include <stdint.h>
19
20 #include "chip.h"
21
22 #define DEBUG_SOR 0
23
24 #define APBDEV_PMC_DPD_SAMPLE (0x20)
25 #define APBDEV_PMC_DPD_SAMPLE_ON_DISABLE (0)
26 #define APBDEV_PMC_DPD_SAMPLE_ON_ENABLE (1)
27 #define APBDEV_PMC_SEL_DPD_TIM (0x1c8)
28 #define APBDEV_PMC_SEL_DPD_TIM_SEL_DPD_TIM_DEFAULT (0x7f)
29 #define APBDEV_PMC_IO_DPD2_REQ (0x1c0)
30 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_SHIFT (25)
31 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF (0 << 25)
32 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_ON (1 << 25)
33 #define APBDEV_PMC_IO_DPD2_REQ_CODE_SHIFT (30)
34 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK (0x3 << 30)
35 #define APBDEV_PMC_IO_DPD2_REQ_CODE_IDLE (0 << 30)
36 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF (1 << 30)
37 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON (2 << 30)
38 #define APBDEV_PMC_IO_DPD2_STATUS (0x1c4)
39 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_SHIFT (25)
40 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_OFF (0 << 25)
41 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON (1 << 25)
42
43 static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg)
44 {
45 void *addr = sor->base + (u32)(reg << 2);
46 u32 reg_val = READL(addr);
47 return reg_val;
48 }
49
50 static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor,
51 u32 reg, u32 val)
52 {
53 void *addr = sor->base + (u32)(reg << 2);
54 WRITEL(val, addr);
55 }
56
57 static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor,
58 u32 reg, u32 mask, u32 val)
59 {
60 u32 reg_val = tegra_sor_readl(sor, reg);
61 reg_val &= ~mask;
62 reg_val |= val;
63 tegra_sor_writel(sor, reg, reg_val);
64 }
65
66 void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor)
67 {
68 tegra_sor_write_field(sor,
69 NV_SOR_DP_PADCTL(sor->portnum),
70 NV_SOR_DP_PADCTL_TX_PU_MASK,
71 NV_SOR_DP_PADCTL_TX_PU_DISABLE);
72 }
73
74 void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask,
75 u32 pe_reg, u32 vs_reg, u32 pc_reg, u8 pc_supported)
76 {
77 tegra_sor_write_field(sor, NV_SOR_PR(sor->portnum),
78 mask, pe_reg);
79 tegra_sor_write_field(sor, NV_SOR_DC(sor->portnum),
80 mask, vs_reg);
81 if (pc_supported) {
82 tegra_sor_write_field(
83 sor, NV_SOR_POSTCURSOR(sor->portnum),
84 mask, pc_reg);
85 }
86 }
87
88 static u32 tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor,
89 u32 reg, u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_us)
90 {
91 u32 temp = timeout_us;
92 u32 reg_val = 0;
93
94 do {
95 udelay(poll_interval_us);
96 reg_val = tegra_sor_readl(sor, reg);
97 if (timeout_us > poll_interval_us)
98 timeout_us -= poll_interval_us;
99 else
100 break;
101 } while ((reg_val & mask) != exp_val);
102
103 if ((reg_val & mask) == exp_val)
104 return 0; /* success */
105 printk(BIOS_ERR,
106 "sor_poll_register 0x%x: timeout, "
107 "(reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n",
108 reg, reg_val, mask, exp_val);
109
110 return temp;
111 }
112
113 int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd)
114 {
115 u32 reg_val;
116 u32 orig_val;
117
118 orig_val = tegra_sor_readl(sor, NV_SOR_PWR);
119
120 reg_val = pu_pd ? NV_SOR_PWR_NORMAL_STATE_PU :
121 NV_SOR_PWR_NORMAL_STATE_PD; /* normal state only */
122
123 if (reg_val == orig_val)
124 return 0; /* No update needed */
125
126 reg_val |= NV_SOR_PWR_SETTING_NEW_TRIGGER;
127 tegra_sor_writel(sor, NV_SOR_PWR, reg_val);
128
129 /* Poll to confirm it is done */
130 if (tegra_dc_sor_poll_register(sor, NV_SOR_PWR,
131 NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK,
132 NV_SOR_PWR_SETTING_NEW_DONE,
133 100, TEGRA_SOR_TIMEOUT_MS * 1000)) {
134 printk(BIOS_ERR,
135 "dc timeout waiting for SOR_PWR = NEW_DONE\n");
136 return -EFAULT;
137 }
138 return 0;
139 }
140
141 void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena,
142 u8 training_pattern, const struct tegra_dc_dp_link_config *link_cfg)
143 {
144 u32 reg_val;
145
146 reg_val = tegra_sor_readl(sor, NV_SOR_DP_LINKCTL(sor->portnum));
147
148 if (ena)
149 reg_val |= NV_SOR_DP_LINKCTL_ENABLE_YES;
150 else
151 reg_val &= NV_SOR_DP_LINKCTL_ENABLE_NO;
152
153 reg_val &= ~NV_SOR_DP_LINKCTL_TUSIZE_MASK;
154 reg_val |= (link_cfg->tu_size << NV_SOR_DP_LINKCTL_TUSIZE_SHIFT);
155
156 if (link_cfg->enhanced_framing)
157 reg_val |= NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE;
158
159 tegra_sor_writel(sor, NV_SOR_DP_LINKCTL(sor->portnum), reg_val);
160
161 switch (training_pattern) {
162 case training_pattern_1:
163 tegra_sor_writel(sor, NV_SOR_DP_TPG, 0x41414141);
164 break;
165 case training_pattern_2:
166 case training_pattern_3:
167 reg_val = (link_cfg->link_bw == SOR_LINK_SPEED_G5_4) ?
168 0x43434343 : 0x42424242;
169 tegra_sor_writel(sor, NV_SOR_DP_TPG, reg_val);
170 break;
171 default:
172 tegra_sor_writel(sor, NV_SOR_DP_TPG, 0x50505050);
173 break;
174 }
175 }
176
177 static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor,
178 int pu, int is_lvds)
179 {
180 u32 reg_val;
181
182 /* SOR lane sequencer */
183 if (pu)
184 reg_val = NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
185 NV_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
186 NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PU;
187 else
188 reg_val = NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
189 NV_SOR_LANE_SEQ_CTL_SEQUENCE_UP |
190 NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PD;
191
192 if (is_lvds)
193 reg_val |= 15 << NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT;
194 else
195 reg_val |= 1 << NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT;
196
197 tegra_sor_writel(sor, NV_SOR_LANE_SEQ_CTL, reg_val);
198
199 if (tegra_dc_sor_poll_register(sor, NV_SOR_LANE_SEQ_CTL,
200 NV_SOR_LANE_SEQ_CTL_SETTING_MASK,
201 NV_SOR_LANE_SEQ_CTL_SETTING_NEW_DONE,
202 100, TEGRA_SOR_TIMEOUT_MS*1000)) {
203 printk(BIOS_ERR,
204 "dp: timeout while waiting for SOR lane sequencer "
205 "to power down langes\n");
206 return -1;
207 }
208 return 0;
209 }
210
211 static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor,
212 u32 lane_count, int pu)
213 {
214 u32 reg_val;
215
216 reg_val = tegra_sor_readl(sor, NV_SOR_DP_PADCTL(sor->portnum));
217
218 if (pu) {
219 switch (lane_count) {
220 case 4:
221 reg_val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO |
222 NV_SOR_DP_PADCTL_PD_TXD_2_NO);
223 __fallthrough;
224 case 2:
225 reg_val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO;
226 __fallthrough;
227 case 1:
228 reg_val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO;
229 break;
230 default:
231 printk(BIOS_ERR,
232 "dp: invalid lane number %d\n", lane_count);
233 return -1;
234 }
235
236 tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), reg_val);
237 tegra_dc_sor_set_lane_count(sor, lane_count);
238 }
239 return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0);
240 }
241
242 void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor,
243 int power_up)
244 {
245 u32 reg_val;
246
247 /* !!TODO: need to enable panel power through GPIO operations */
248 /* Check bug 790854 for HW progress */
249
250 reg_val = tegra_sor_readl(sor, NV_SOR_DP_PADCTL(sor->portnum));
251
252 if (power_up)
253 reg_val |= NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERUP;
254 else
255 reg_val &= ~NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERUP;
256
257 tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), reg_val);
258 }
259
260 static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div,
261 u32 pwm_dutycycle)
262 {
263 tegra_sor_writel(sor, NV_SOR_PWM_DIV, pwm_div);
264 tegra_sor_writel(sor, NV_SOR_PWM_CTL,
265 (pwm_dutycycle & NV_SOR_PWM_CTL_DUTY_CYCLE_MASK) |
266 NV_SOR_PWM_CTL_SETTING_NEW_TRIGGER);
267
268 if (tegra_dc_sor_poll_register(sor, NV_SOR_PWM_CTL,
269 NV_SOR_PWM_CTL_SETTING_NEW_SHIFT,
270 NV_SOR_PWM_CTL_SETTING_NEW_DONE,
271 100, TEGRA_SOR_TIMEOUT_MS * 1000)) {
272 printk(BIOS_ERR,
273 "dp: timeout while waiting for SOR PWM setting\n");
274 }
275 }
276
277 static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor,
278 const struct tegra_dc_dp_link_config *link_cfg)
279 {
280 u32 reg_val;
281
282 tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
283
284 tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_none, link_cfg);
285 reg_val = tegra_sor_readl(sor, NV_SOR_DP_CONFIG(sor->portnum));
286 reg_val &= ~NV_SOR_DP_CONFIG_WATERMARK_MASK;
287 reg_val |= link_cfg->watermark;
288 reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK;
289 reg_val |= (link_cfg->active_count <<
290 NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_SHIFT);
291 reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK;
292 reg_val |= (link_cfg->active_frac <<
293 NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_SHIFT);
294 if (link_cfg->activepolarity)
295 reg_val |= NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
296 else
297 reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
298 reg_val |= (NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE |
299 NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE);
300
301 tegra_sor_writel(sor, NV_SOR_DP_CONFIG(sor->portnum), reg_val);
302
303 /* program h/vblank sym */
304 tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_HBLANK_SYMBOLS,
305 NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK, link_cfg->hblank_sym);
306
307 tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_VBLANK_SYMBOLS,
308 NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK, link_cfg->vblank_sym);
309 }
310
311 static inline void tegra_dc_sor_super_update(struct tegra_dc_sor_data *sor)
312 {
313 tegra_sor_writel(sor, NV_SOR_SUPER_STATE0, 0);
314 tegra_sor_writel(sor, NV_SOR_SUPER_STATE0, 1);
315 tegra_sor_writel(sor, NV_SOR_SUPER_STATE0, 0);
316 }
317
318 static inline void tegra_dc_sor_update(struct tegra_dc_sor_data *sor)
319 {
320 tegra_sor_writel(sor, NV_SOR_STATE0, 0);
321 tegra_sor_writel(sor, NV_SOR_STATE0, 1);
322 tegra_sor_writel(sor, NV_SOR_STATE0, 0);
323 }
324
325 static void tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, int up)
326 {
327 u32 reg_val;
328 void *pmc_base = sor->pmc_base;
329
330 if (up) {
331 WRITEL(APBDEV_PMC_DPD_SAMPLE_ON_ENABLE,
332 pmc_base + APBDEV_PMC_DPD_SAMPLE);
333 WRITEL(10, pmc_base + APBDEV_PMC_SEL_DPD_TIM);
334 }
335
336 reg_val = READL(pmc_base + APBDEV_PMC_IO_DPD2_REQ);
337 reg_val &= ~(APBDEV_PMC_IO_DPD2_REQ_LVDS_ON |
338 APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK);
339
340 reg_val |= up ? APBDEV_PMC_IO_DPD2_REQ_LVDS_ON |
341 APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF :
342 APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF |
343 APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON;
344
345 WRITEL(reg_val, pmc_base + APBDEV_PMC_IO_DPD2_REQ);
346
347 /* Polling */
348 u32 temp = 10*1000;
349 do {
350 udelay(20);
351 reg_val = READL(pmc_base + APBDEV_PMC_IO_DPD2_STATUS);
352 if (temp > 20)
353 temp -= 20;
354 else
355 break;
356 } while ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0);
357
358 if ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0)
359 printk(BIOS_ERR,
360 "PMC_IO_DPD2 polling failed (0x%x)\n", reg_val);
361
362 if (up)
363 WRITEL(APBDEV_PMC_DPD_SAMPLE_ON_DISABLE,
364 pmc_base + APBDEV_PMC_DPD_SAMPLE);
365 }
366
367 void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int)
368 {
369 u32 reg_val;
370
371 reg_val = tegra_sor_readl(sor, NV_SOR_DP_SPARE(sor->portnum));
372 if (is_int)
373 reg_val |= NV_SOR_DP_SPARE_PANEL_INTERNAL;
374 else
375 reg_val &= ~NV_SOR_DP_SPARE_PANEL_INTERNAL;
376
377 reg_val |= NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK |
378 NV_SOR_DP_SPARE_SEQ_ENABLE_YES;
379 tegra_sor_writel(sor, NV_SOR_DP_SPARE(sor->portnum), reg_val);
380 }
381
382 void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw,
383 u8 *lane_count)
384 {
385 u32 reg_val;
386
387 reg_val = tegra_sor_readl(sor, NV_SOR_CLK_CNTRL);
388 *link_bw = (reg_val & NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK)
389 >> NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT;
390 reg_val = tegra_sor_readl(sor,
391 NV_SOR_DP_LINKCTL(sor->portnum));
392
393 switch (reg_val & NV_SOR_DP_LINKCTL_LANECOUNT_MASK) {
394 case NV_SOR_DP_LINKCTL_LANECOUNT_ZERO:
395 *lane_count = 0;
396 break;
397 case NV_SOR_DP_LINKCTL_LANECOUNT_ONE:
398 *lane_count = 1;
399 break;
400 case NV_SOR_DP_LINKCTL_LANECOUNT_TWO:
401 *lane_count = 2;
402 break;
403 case NV_SOR_DP_LINKCTL_LANECOUNT_FOUR:
404 *lane_count = 4;
405 break;
406 default:
407 printk(BIOS_ERR, "Unknown lane count\n");
408 }
409 }
410
411 void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw)
412 {
413 tegra_sor_write_field(sor, NV_SOR_CLK_CNTRL,
414 NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK,
415 link_bw << NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT);
416 }
417
418 void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count)
419 {
420 u32 reg_val;
421
422 reg_val = tegra_sor_readl(sor, NV_SOR_DP_LINKCTL(sor->portnum));
423 reg_val &= ~NV_SOR_DP_LINKCTL_LANECOUNT_MASK;
424 switch (lane_count) {
425 case 0:
426 break;
427 case 1:
428 reg_val |= NV_SOR_DP_LINKCTL_LANECOUNT_ONE;
429 break;
430 case 2:
431 reg_val |= NV_SOR_DP_LINKCTL_LANECOUNT_TWO;
432 break;
433 case 4:
434 reg_val |= NV_SOR_DP_LINKCTL_LANECOUNT_FOUR;
435 break;
436 default:
437 /* 0 should be handled earlier. */
438 printk(BIOS_ERR, "dp: Invalid lane count %d\n",
439 lane_count);
440 return;
441 }
442 tegra_sor_writel(sor, NV_SOR_DP_LINKCTL(sor->portnum), reg_val);
443 }
444
445 static void tegra_sor_enable_edp_clock(struct tegra_dc_sor_data *sor)
446 {
447 sor_clock_start();
448 }
449
450 /* The SOR power sequencer does not work for t124 so SW has to
451 go through the power sequence manually */
452 /* Power up steps from spec: */
453 /* STEP PDPORT PDPLL PDBG PLLVCOD PLLCAPD E_DPD PDCAL */
454 /* 1 1 1 1 1 1 1 1 */
455 /* 2 1 1 1 1 1 0 1 */
456 /* 3 1 1 0 1 1 0 1 */
457 /* 4 1 0 0 0 0 0 1 */
458 /* 5 0 0 0 0 0 0 1 */
459 static void tegra_dc_sor_power_up(struct tegra_dc_sor_data *sor,
460 int is_lvds)
461 {
462 if (sor->power_is_up)
463 return;
464
465 /* Set link bw */
466 tegra_dc_sor_set_link_bandwidth(sor,
467 is_lvds ? NV_SOR_CLK_CNTRL_DP_LINK_SPEED_LVDS :
468 NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62);
469
470 /* step 1 */
471 tegra_sor_write_field(sor, NV_SOR_PLL2,
472 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK | /* PDPORT */
473 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK | /* PDBG */
474 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
475 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE |
476 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE |
477 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE);
478 tegra_sor_write_field(sor, NV_SOR_PLL0,
479 NV_SOR_PLL0_PWR_MASK | /* PDPLL */
480 NV_SOR_PLL0_VCOPD_MASK, /* PLLVCOPD */
481 NV_SOR_PLL0_PWR_OFF |
482 NV_SOR_PLL0_VCOPD_ASSERT);
483 tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
484 NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN, /* PDCAL */
485 NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN);
486
487 /* step 2 */
488 tegra_dc_sor_io_set_dpd(sor, 1);
489 udelay(15);
490
491 /* step 3 */
492 tegra_sor_write_field(sor, NV_SOR_PLL2,
493 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
494 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
495 udelay(25);
496
497 /* step 4 */
498 tegra_sor_write_field(sor, NV_SOR_PLL0,
499 NV_SOR_PLL0_PWR_MASK | /* PDPLL */
500 NV_SOR_PLL0_VCOPD_MASK, /* PLLVCOPD */
501 NV_SOR_PLL0_PWR_ON | NV_SOR_PLL0_VCOPD_RESCIND);
502 tegra_sor_write_field(sor, NV_SOR_PLL2,
503 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
504 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
505 udelay(225);
506
507 /* step 5 */
508 tegra_sor_write_field(sor, NV_SOR_PLL2,
509 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK, /* PDPORT */
510 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE);
511
512 sor->power_is_up = 1;
513 }
514
515 #if DEBUG_SOR
516 static void dump_sor_reg(struct tegra_dc_sor_data *sor)
517 {
518 #define DUMP_REG(a) printk(BIOS_INFO, "%-32s %03x %08x\n", \
519 #a, a, tegra_sor_readl(sor, a))
520
521 DUMP_REG(NV_SOR_SUPER_STATE0);
522 DUMP_REG(NV_SOR_SUPER_STATE1);
523 DUMP_REG(NV_SOR_STATE0);
524 DUMP_REG(NV_SOR_STATE1);
525 DUMP_REG(NV_HEAD_STATE0(0));
526 DUMP_REG(NV_HEAD_STATE0(1));
527 DUMP_REG(NV_HEAD_STATE1(0));
528 DUMP_REG(NV_HEAD_STATE1(1));
529 DUMP_REG(NV_HEAD_STATE2(0));
530 DUMP_REG(NV_HEAD_STATE2(1));
531 DUMP_REG(NV_HEAD_STATE3(0));
532 DUMP_REG(NV_HEAD_STATE3(1));
533 DUMP_REG(NV_HEAD_STATE4(0));
534 DUMP_REG(NV_HEAD_STATE4(1));
535 DUMP_REG(NV_HEAD_STATE5(0));
536 DUMP_REG(NV_HEAD_STATE5(1));
537 DUMP_REG(NV_SOR_CRC_CNTRL);
538 DUMP_REG(NV_SOR_CLK_CNTRL);
539 DUMP_REG(NV_SOR_CAP);
540 DUMP_REG(NV_SOR_PWR);
541 DUMP_REG(NV_SOR_TEST);
542 DUMP_REG(NV_SOR_PLL0);
543 DUMP_REG(NV_SOR_PLL1);
544 DUMP_REG(NV_SOR_PLL2);
545 DUMP_REG(NV_SOR_PLL3);
546 DUMP_REG(NV_SOR_CSTM);
547 DUMP_REG(NV_SOR_LVDS);
548 DUMP_REG(NV_SOR_CRCA);
549 DUMP_REG(NV_SOR_CRCB);
550 DUMP_REG(NV_SOR_SEQ_CTL);
551 DUMP_REG(NV_SOR_LANE_SEQ_CTL);
552 DUMP_REG(NV_SOR_SEQ_INST(0));
553 DUMP_REG(NV_SOR_SEQ_INST(1));
554 DUMP_REG(NV_SOR_SEQ_INST(2));
555 DUMP_REG(NV_SOR_SEQ_INST(3));
556 DUMP_REG(NV_SOR_SEQ_INST(4));
557 DUMP_REG(NV_SOR_SEQ_INST(5));
558 DUMP_REG(NV_SOR_SEQ_INST(6));
559 DUMP_REG(NV_SOR_SEQ_INST(7));
560 DUMP_REG(NV_SOR_SEQ_INST(8));
561 DUMP_REG(NV_SOR_PWM_DIV);
562 DUMP_REG(NV_SOR_PWM_CTL);
563 DUMP_REG(NV_SOR_MSCHECK);
564 DUMP_REG(NV_SOR_XBAR_CTRL);
565 DUMP_REG(NV_SOR_DP_LINKCTL(0));
566 DUMP_REG(NV_SOR_DP_LINKCTL(1));
567 DUMP_REG(NV_SOR_DC(0));
568 DUMP_REG(NV_SOR_DC(1));
569 DUMP_REG(NV_SOR_LANE_DRIVE_CURRENT(0));
570 DUMP_REG(NV_SOR_PR(0));
571 DUMP_REG(NV_SOR_LANE4_PREEMPHASIS(0));
572 DUMP_REG(NV_SOR_POSTCURSOR(0));
573 DUMP_REG(NV_SOR_DP_CONFIG(0));
574 DUMP_REG(NV_SOR_DP_CONFIG(1));
575 DUMP_REG(NV_SOR_DP_MN(0));
576 DUMP_REG(NV_SOR_DP_MN(1));
577 DUMP_REG(NV_SOR_DP_PADCTL(0));
578 DUMP_REG(NV_SOR_DP_PADCTL(1));
579 DUMP_REG(NV_SOR_DP_DEBUG(0));
580 DUMP_REG(NV_SOR_DP_DEBUG(1));
581 DUMP_REG(NV_SOR_DP_SPARE(0));
582 DUMP_REG(NV_SOR_DP_SPARE(1));
583 DUMP_REG(NV_SOR_DP_TPG);
584 }
585 #endif
586
587 static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
588 int is_lvds)
589 {
590 const struct tegra_dc *dc = sor->dc;
591 const struct tegra_dc_dp_data *dp = dc->out;
592 const struct tegra_dc_dp_link_config *link_cfg = &dp->link_cfg;
593 const struct soc_nvidia_tegra124_config *config = dc->config;
594
595 const int head_num = 0; // based on kernel dc driver
596 u32 reg_val = NV_SOR_STATE1_ASY_OWNER_HEAD0 << head_num;
597 u32 vtotal, htotal;
598 u32 vsync_end, hsync_end;
599 u32 vblank_end, hblank_end;
600 u32 vblank_start, hblank_start;
601
602 reg_val |= is_lvds ? NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM :
603 NV_SOR_STATE1_ASY_PROTOCOL_DP_A;
604 reg_val |= NV_SOR_STATE1_ASY_SUBOWNER_NONE |
605 NV_SOR_STATE1_ASY_CRCMODE_COMPLETE_RASTER;
606
607 reg_val |= NV_SOR_STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE;
608 reg_val |= NV_SOR_STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE;
609 reg_val |= (link_cfg->bits_per_pixel > 18) ?
610 NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_444 :
611 NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_444;
612
613 tegra_sor_writel(sor, NV_SOR_STATE1, reg_val);
614
615 /* Skipping programming NV_HEAD_STATE0, assuming:
616 interlacing: PROGRESSIVE, dynamic range: VESA, colorspace: RGB */
617
618 vtotal = config->vsync_width + config->vback_porch +
619 config->yres + config->vfront_porch;
620 htotal = config->hsync_width + config->hback_porch +
621 config->xres + config->hfront_porch;
622
623 tegra_sor_writel(sor, NV_HEAD_STATE1(head_num),
624 vtotal << NV_HEAD_STATE1_VTOTAL_SHIFT |
625 htotal << NV_HEAD_STATE1_HTOTAL_SHIFT);
626
627 vsync_end = config->vsync_width - 1;
628 hsync_end = config->hsync_width - 1;
629 tegra_sor_writel(sor, NV_HEAD_STATE2(head_num),
630 vsync_end << NV_HEAD_STATE2_VSYNC_END_SHIFT |
631 hsync_end << NV_HEAD_STATE2_HSYNC_END_SHIFT);
632
633 vblank_end = vsync_end + config->vback_porch;
634 hblank_end = hsync_end + config->hback_porch;
635 tegra_sor_writel(sor, NV_HEAD_STATE3(head_num),
636 vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT |
637 hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT);
638
639 vblank_start = vblank_end + config->yres;
640 hblank_start = hblank_end + config->xres;
641 tegra_sor_writel(sor, NV_HEAD_STATE4(head_num),
642 vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT |
643 hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT);
644
645 /* TODO: adding interlace mode support */
646 tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1);
647
648 tegra_sor_write_field(sor, NV_SOR_CSTM,
649 NV_SOR_CSTM_ROTCLK_DEFAULT_MASK |
650 NV_SOR_CSTM_LVDS_EN_ENABLE,
651 2 << NV_SOR_CSTM_ROTCLK_SHIFT |
652 (is_lvds ? NV_SOR_CSTM_LVDS_EN_ENABLE :
653 NV_SOR_CSTM_LVDS_EN_DISABLE));
654 tegra_dc_sor_config_pwm(sor, 1024, 1024);
655 }
656
657 static void tegra_dc_sor_enable_dc(struct tegra_dc_sor_data *sor)
658 {
659 struct tegra_dc *dc = sor->dc;
660 struct display_controller *disp_ctrl = (void *)dc->base;
661
662 u32 reg_val = READL(&disp_ctrl->cmd.state_access);
663
664 WRITEL(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
665 WRITEL(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt);
666
667 /* Enable DC now - otherwise pure text console may not show. */
668 WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd);
669 WRITEL(reg_val, &disp_ctrl->cmd.state_access);
670 }
671
672 void tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor)
673 {
674 const struct tegra_dc_dp_link_config *link_cfg = sor->link_cfg;
675
676 tegra_sor_write_field(sor, NV_SOR_CLK_CNTRL,
677 NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK,
678 NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK);
679
680 tegra_sor_write_field(sor, NV_SOR_PLL2,
681 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
682 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
683 udelay(25);
684
685 tegra_sor_write_field(sor, NV_SOR_PLL3,
686 NV_SOR_PLL3_PLLVDD_MODE_MASK,
687 NV_SOR_PLL3_PLLVDD_MODE_V3_3);
688 tegra_sor_writel(sor, NV_SOR_PLL0,
689 0xf << NV_SOR_PLL0_ICHPMP_SHFIT |
690 0x3 << NV_SOR_PLL0_VCOCAP_SHIFT |
691 NV_SOR_PLL0_PLLREG_LEVEL_V45 |
692 NV_SOR_PLL0_RESISTORSEL_EXT |
693 NV_SOR_PLL0_PWR_ON | NV_SOR_PLL0_VCOPD_RESCIND);
694 tegra_sor_write_field(sor, NV_SOR_PLL2,
695 NV_SOR_PLL2_AUX1_SEQ_MASK | NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE |
696 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
697 NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
698 NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE |
699 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
700 tegra_sor_writel(sor, NV_SOR_PLL1,
701 NV_SOR_PLL1_TERM_COMPOUT_HIGH | NV_SOR_PLL1_TMDS_TERM_ENABLE);
702
703 if (tegra_dc_sor_poll_register(sor, NV_SOR_PLL2,
704 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
705 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE,
706 100, TEGRA_SOR_TIMEOUT_MS * 1000)) {
707 printk(BIOS_ERR, "DP failed to lock PLL\n");
708 return;
709 }
710
711 tegra_sor_write_field(sor, NV_SOR_PLL2,
712 NV_SOR_PLL2_AUX2_MASK | NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK,
713 NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN |
714 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE);
715
716 tegra_dc_sor_power_up(sor, 0);
717
718 /* re-enable SOR clock */
719 tegra_sor_enable_edp_clock(sor); // select pll_dp as clock source
720
721 /* Power up lanes */
722 tegra_dc_sor_power_dplanes(sor, link_cfg->lane_count, 1);
723
724 tegra_dc_sor_set_dp_mode(sor, link_cfg);
725 }
726
727 void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor)
728 {
729 u32 reg_val;
730 struct display_controller *disp_ctrl = (void *)sor->dc->base;
731
732 tegra_dc_sor_enable_dc(sor);
733 tegra_dc_sor_config_panel(sor, 0);
734
735 WRITEL(0x9f00, &disp_ctrl->cmd.state_ctrl);
736 WRITEL(0x9f, &disp_ctrl->cmd.state_ctrl);
737
738 WRITEL(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE |
739 PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
740 &disp_ctrl->cmd.disp_pow_ctrl);
741
742 reg_val = tegra_sor_readl(sor, NV_SOR_TEST);
743 if (reg_val & NV_SOR_TEST_ATTACHED_TRUE)
744 return;
745
746 tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
747 NV_SOR_SUPER_STATE1_ATTACHED_NO);
748
749 /*
750 * Enable display2sor clock at least 2 cycles before DC start,
751 * to clear sor internal valid signal.
752 */
753 WRITEL(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
754 WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
755 WRITEL(0, &disp_ctrl->disp.disp_win_opt);
756 WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
757
758 /* Attach head */
759 tegra_dc_sor_update(sor);
760 tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
761 NV_SOR_SUPER_STATE1_ATTACHED_YES);
762 tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
763 NV_SOR_SUPER_STATE1_ATTACHED_YES |
764 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE |
765 NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL);
766 tegra_dc_sor_super_update(sor);
767
768 /* Enable dc */
769 reg_val = READL(&disp_ctrl->cmd.state_access);
770 WRITEL(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
771 WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd);
772 WRITEL(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
773 WRITEL(reg_val, &disp_ctrl->cmd.state_access);
774
775 if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
776 NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
777 NV_SOR_TEST_ACT_HEAD_OPMODE_AWAKE,
778 100, TEGRA_SOR_ATTACH_TIMEOUT_MS * 1000))
779 printk(BIOS_ERR, "dc timeout waiting for OPMOD = AWAKE\n");
780 else
781 printk(BIOS_INFO, "%s: sor is attached\n", __func__);
782
783 #if DEBUG_SOR
784 dump_sor_reg(sor);
785 #endif
786 }
787
788 void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor,
789 const struct tegra_dc_dp_link_config *link_cfg)
790 {
791 tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum),
792 link_cfg->drive_current);
793 tegra_sor_writel(sor, NV_SOR_PR(sor->portnum),
794 link_cfg->preemphasis);
795 tegra_sor_writel(sor, NV_SOR_POSTCURSOR(sor->portnum),
796 link_cfg->postcursor);
797 tegra_sor_writel(sor, NV_SOR_LVDS, 0);
798
799 tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
800 tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count);
801
802 tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
803 NV_SOR_DP_PADCTL_TX_PU_ENABLE |
804 NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK,
805 NV_SOR_DP_PADCTL_TX_PU_ENABLE |
806 2 << NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT);
807
808 /* Precharge */
809 tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
810 0xf0, 0xf0);
811 udelay(20);
812
813 tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
814 0xf0, 0x0);
815 }
816
817 void tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor)
818 {
819 u32 drive_current = 0;
820 u32 pre_emphasis = 0;
821
822 /* Set to a known-good pre-calibrated setting */
823 switch (sor->link_cfg->link_bw) {
824 case SOR_LINK_SPEED_G1_62:
825 case SOR_LINK_SPEED_G2_7:
826 drive_current = 0x13131313;
827 pre_emphasis = 0;
828 break;
829 case SOR_LINK_SPEED_G5_4:
830 printk(BIOS_WARNING, "T124 does not support 5.4G link clock.\n");
831 return;
832 default:
833 printk(BIOS_WARNING, "Invalid sor link bandwidth: %d\n",
834 sor->link_cfg->link_bw);
835 return;
836 }
837
838 tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum),
839 drive_current);
840 tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), pre_emphasis);
841 }
842
843 void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor)
844 {
845 u32 pad_ctrl = 0;
846 int err = 0;
847
848 switch (sor->link_cfg->lane_count) {
849 case 4:
850 pad_ctrl = (NV_SOR_DP_PADCTL_PD_TXD_0_NO |
851 NV_SOR_DP_PADCTL_PD_TXD_1_NO |
852 NV_SOR_DP_PADCTL_PD_TXD_2_NO |
853 NV_SOR_DP_PADCTL_PD_TXD_3_NO);
854 break;
855 case 2:
856 pad_ctrl = (NV_SOR_DP_PADCTL_PD_TXD_0_NO |
857 NV_SOR_DP_PADCTL_PD_TXD_1_NO |
858 NV_SOR_DP_PADCTL_PD_TXD_2_YES |
859 NV_SOR_DP_PADCTL_PD_TXD_3_YES);
860 break;
861 case 1:
862 pad_ctrl = (NV_SOR_DP_PADCTL_PD_TXD_0_NO |
863 NV_SOR_DP_PADCTL_PD_TXD_1_YES |
864 NV_SOR_DP_PADCTL_PD_TXD_2_YES |
865 NV_SOR_DP_PADCTL_PD_TXD_3_YES);
866 break;
867 default:
868 printk(BIOS_ERR, "Invalid sor lane count: %u\n",
869 sor->link_cfg->lane_count);
870 return;
871 }
872
873 pad_ctrl |= NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN;
874 tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), pad_ctrl);
875
876 err = tegra_dc_sor_enable_lane_sequencer(sor, 0, 0);
877 if (err) {
878 printk(BIOS_ERR,
879 "Wait for lane power down failed: %d\n", err);
880 return;
881 }
882 }
883
884 void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor)
885 {
886 const struct tegra_dc_dp_link_config *cfg = sor->link_cfg;
887 u32 val = 0;
888
889 switch (cfg->lane_count) {
890 case 4:
891 val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO |
892 NV_SOR_DP_PADCTL_PD_TXD_2_NO);
893 __fallthrough;
894 case 2:
895 val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO;
896 __fallthrough;
897 case 1:
898 val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO;
899 break;
900 default:
901 printk(BIOS_ERR,
902 "dp: invalid lane number %d\n", cfg->lane_count);
903 return;
904 }
905
906 tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
907 (0xf << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT),
908 (val << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT));
909 udelay(100);
910 tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
911 (0xf << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT), 0);
912 }
coreboot repo mirror