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[coreboot2.git] / src / soc / rockchip / rk3399 / gpio.c
blob8c6698757824b5426237317856af8431bae8d897
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <gpio.h>
4 #include <soc/addressmap.h>
5 #include <soc/grf.h>
6 #include <soc/soc.h>
8 struct rockchip_gpio_regs *gpio_port[] = {
9 (struct rockchip_gpio_regs *)GPIO0_BASE,
10 (struct rockchip_gpio_regs *)GPIO1_BASE,
11 (struct rockchip_gpio_regs *)GPIO2_BASE,
12 (struct rockchip_gpio_regs *)GPIO3_BASE,
13 (struct rockchip_gpio_regs *)GPIO4_BASE,
16 #define PMU_GPIO_PORT0 0
17 #define PMU_GPIO_PORT1 1
19 int is_pmu_gpio(gpio_t gpio)
21 if (gpio.port == PMU_GPIO_PORT0 || gpio.port == PMU_GPIO_PORT1)
22 return 1;
23 return 0;
26 void *gpio_grf_reg(gpio_t gpio)
28 if (is_pmu_gpio(gpio))
29 return &rk3399_pmugrf->gpio0_p[gpio.port][gpio.bank];
30 /* There are two pmu gpio, 0 and 1, so " - 2" */
31 return &rk3399_grf->gpio2_p[(gpio.port - 2)][gpio.bank];
34 #define IS_GPIO_BANK(g, p, b) (g.port == p && g.bank == GPIO_##b)
36 enum {
37 PULLNONE_1V8 = 0,
38 PULLDOWN_1V8 = 1,
39 PULLUP_1V8 = 3,
42 u32 gpio_get_pull_val(gpio_t gpio, enum gpio_pull pull)
44 /* The default pull bias setting defined in soc/gpio.h */
45 u32 pull_val = pull;
47 /* GPIO0_A, GPIO0_B, GPIO2_C, GPIO2_D use the 1V8 pull bias setting.
48 * Defined in TRM V.03 Part1 Page 331 and Page 458
50 if (IS_GPIO_BANK(gpio, 0, A) || IS_GPIO_BANK(gpio, 0, B) ||
51 IS_GPIO_BANK(gpio, 2, C) || IS_GPIO_BANK(gpio, 2, D)) {
52 switch (pull) {
53 case GPIO_PULLUP:
54 pull_val = PULLUP_1V8;
55 break;
56 case GPIO_PULLDOWN:
57 pull_val = PULLDOWN_1V8;
58 break;
59 case GPIO_PULLNONE:
60 pull_val = PULLNONE_1V8;
64 return pull_val;