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docs: Add 24.12 release notes
[coreboot2.git] / src / soc / rockchip / rk3399 / sdram.c
blobbe1da598a8c82098e7429d7094db02542a3ee98c
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/mmio.h>
4 #include <console/console.h>
5 #include <delay.h>
6 #include <reset.h>
7 #include <soc/addressmap.h>
8 #include <soc/clock.h>
9 #include <soc/sdram.h>
10 #include <soc/grf.h>
11 #include <soc/soc.h>
12 #include <timer.h>
13 #include <types.h>
14
15 #define DDR_PI_OFFSET 0x800
16 #define DDR_PHY_OFFSET 0x2000
17 #define DDRC0_PI_BASE_ADDR (DDRC0_BASE_ADDR + DDR_PI_OFFSET)
18 #define DDRC0_PHY_BASE_ADDR (DDRC0_BASE_ADDR + DDR_PHY_OFFSET)
19 #define DDRC1_PI_BASE_ADDR (DDRC1_BASE_ADDR + DDR_PI_OFFSET)
20 #define DDRC1_PHY_BASE_ADDR (DDRC1_BASE_ADDR + DDR_PHY_OFFSET)
21
22 static struct rk3399_ddr_pctl_regs * const rk3399_ddr_pctl[2] = {
23 (void *)DDRC0_BASE_ADDR, (void *)DDRC1_BASE_ADDR };
24 static struct rk3399_ddr_pi_regs * const rk3399_ddr_pi[2] = {
25 (void *)DDRC0_PI_BASE_ADDR, (void *)DDRC1_PI_BASE_ADDR };
26 static struct rk3399_ddr_publ_regs * const rk3399_ddr_publ[2] = {
27 (void *)DDRC0_PHY_BASE_ADDR, (void *)DDRC1_PHY_BASE_ADDR };
28 static struct rk3399_msch_regs * const rk3399_msch[2] = {
29 (void *)SERVER_MSCH0_BASE_ADDR, (void *)SERVER_MSCH1_BASE_ADDR };
30 static struct rk3399_ddr_cic_regs *const rk3399_ddr_cic = (void *)CIC_BASE_ADDR;
31
32 /*
33 * sys_reg bitfield struct
34 * [31] row_3_4_ch1
35 * [30] row_3_4_ch0
36 * [29:28] chinfo
37 * [27] rank_ch1
38 * [26:25] col_ch1
39 * [24] bk_ch1
40 * [23:22] cs0_row_ch1
41 * [21:20] cs1_row_ch1
42 * [19:18] bw_ch1
43 * [17:16] dbw_ch1;
44 * [15:13] ddrtype
45 * [12] channelnum
46 * [11] rank_ch0
47 * [10:9] col_ch0
48 * [8] bk_ch0
49 * [7:6] cs0_row_ch0
50 * [5:4] cs1_row_ch0
51 * [3:2] bw_ch0
52 * [1:0] dbw_ch0
53 */
54 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
55 #define SYS_REG_DEC_ROW_3_4(n, ch) ((n >> (30 + ch)) & 0x1)
56 #define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch)))
57 #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
58 #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12)
59 #define SYS_REG_DEC_NUM_CH(n) (1 + ((n >> 12) & 0x1))
60 #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + ((ch) * 16)))
61 #define SYS_REG_DEC_RANK(n, ch) (1 + ((n >> (11 + 16 * ch)) & 0x1))
62 #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16)))
63 #define SYS_REG_DEC_COL(n, ch) (9 + ((n >> (9 + 16 * ch)) & 0x3))
64 #define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) \
65 << (8 + ((ch) * 16)))
66 #define SYS_REG_DEC_BK(n, ch) (3 - ((n >> (8 + 16 * ch)) & 0x1))
67 #define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << (6 + ((ch) * 16)))
68 #define SYS_REG_DEC_CS0_ROW(n, ch) (13 + ((n >> (6 + 16 * ch)) & 0x3))
69 #define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << (4 + ((ch) * 16)))
70 #define SYS_REG_DEC_CS1_ROW(n, ch) (13 + ((n >> (4 + 16 * ch)) & 0x3))
71 #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + ((ch) * 16)))
72 #define SYS_REG_DEC_BW(n, ch) (2 >> ((n >> (2 + 16 * ch)) & 0x3))
73 #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16)))
74 #define SYS_REG_DEC_DBW(n, ch) (2 >> ((n >> (0 + 16 * ch)) & 0x3))
75
76 #define DDR_STRIDE(n) write32(&rk3399_pmusgrf->soc_con4,\
77 (0x1F << (10 + 16)) | (n << 10))
78
79 #define PRESET_SGRF_HOLD(n) ((0x1 << (6+16)) | ((n) << 6))
80 #define PRESET_GPIO0_HOLD(n) ((0x1 << (7+16)) | ((n) << 7))
81 #define PRESET_GPIO1_HOLD(n) ((0x1 << (8+16)) | ((n) << 8))
82
83 #define PHY_DRV_ODT_Hi_Z (0x0)
84 #define PHY_DRV_ODT_240 (0x1)
85 #define PHY_DRV_ODT_120 (0x8)
86 #define PHY_DRV_ODT_80 (0x9)
87 #define PHY_DRV_ODT_60 (0xc)
88 #define PHY_DRV_ODT_48 (0xd)
89 #define PHY_DRV_ODT_40 (0xe)
90 #define PHY_DRV_ODT_34_3 (0xf)
91
92 #define MAX_RANKS_PER_CHANNEL 4
93
94 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
95 {
96 int i;
97
98 for (i = 0; i < n / sizeof(u32); i++) {
99 write32(dest, *src);
100 src++;
101 dest++;
102 }
103 }
104
105 static void phy_pctrl_reset(u32 channel)
106 {
107 rkclk_ddr_reset(channel, 1, 1);
108 udelay(10);
109
110 rkclk_ddr_reset(channel, 1, 0);
111 udelay(10);
112
113 rkclk_ddr_reset(channel, 0, 0);
114 udelay(10);
115 }
116
117 static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
118 u32 freq)
119 {
120 u32 *denali_phy = ddr_publ_regs->denali_phy;
121
122 if (freq <= 125*MHz) {
123 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
124 setbits32(&denali_phy[86], (0x3 << 2) << 8);
125 setbits32(&denali_phy[214], (0x3 << 2) << 8);
126 setbits32(&denali_phy[342], (0x3 << 2) << 8);
127 setbits32(&denali_phy[470], (0x3 << 2) << 8);
128
129 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
130 setbits32(&denali_phy[547], (0x3 << 2) << 16);
131 setbits32(&denali_phy[675], (0x3 << 2) << 16);
132 setbits32(&denali_phy[803], (0x3 << 2) << 16);
133 } else {
134 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
135 clrbits32(&denali_phy[86], (0x3 << 2) << 8);
136 clrbits32(&denali_phy[214], (0x3 << 2) << 8);
137 clrbits32(&denali_phy[342], (0x3 << 2) << 8);
138 clrbits32(&denali_phy[470], (0x3 << 2) << 8);
139
140 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
141 clrbits32(&denali_phy[547], (0x3 << 2) << 16);
142 clrbits32(&denali_phy[675], (0x3 << 2) << 16);
143 clrbits32(&denali_phy[803], (0x3 << 2) << 16);
144 }
145 }
146
147 static void set_memory_map(u32 channel, const struct rk3399_sdram_params *params)
148 {
149 const struct rk3399_sdram_channel *sdram_ch = &params->ch[channel];
150 u32 *denali_ctl = rk3399_ddr_pctl[channel]->denali_ctl;
151 u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi;
152 u32 cs_map;
153 u32 reduc;
154 u32 row;
155
156 if ((sdram_ch->ddrconfig < 2) || (sdram_ch->ddrconfig == 4))
157 row = 16;
158 else if (sdram_ch->ddrconfig == 3)
159 row = 14;
160 else
161 row = 15;
162
163 cs_map = (sdram_ch->rank > 1) ? 3 : 1;
164 reduc = (sdram_ch->bw == 2) ? 0 : 1;
165
166 clrsetbits32(&denali_ctl[191], 0xF, (12 - sdram_ch->col));
167 clrsetbits32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
168 ((3 - sdram_ch->bk) << 16) |
169 ((16 - row) << 24));
170
171 clrsetbits32(&denali_ctl[196], 0x3 | (1 << 16),
172 cs_map | (reduc << 16));
173
174 /* PI_199 PI_COL_DIFF:RW:0:4 */
175 clrsetbits32(&denali_pi[199], 0xF, (12 - sdram_ch->col));
176
177 /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
178 clrsetbits32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
179 ((3 - sdram_ch->bk) << 16) |
180 ((16 - row) << 24));
181 /* PI_41 PI_CS_MAP:RW:24:4 */
182 clrsetbits32(&denali_pi[41], 0xf << 24, cs_map << 24);
183 if ((sdram_ch->rank == 1) && (params->dramtype == DDR3))
184 write32(&denali_pi[34], 0x2EC7FFFF);
185 }
186
187 static void set_ds_odt(u32 channel, const struct rk3399_sdram_params *params)
188 {
189 u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
190
191 u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
192 u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p;
193 u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n;
194 u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n;
195 u32 reg_value;
196
197 if (params->dramtype == LPDDR4) {
198 tsel_rd_select_p = PHY_DRV_ODT_Hi_Z;
199 tsel_rd_select_n = PHY_DRV_ODT_240;
200
201 tsel_wr_select_p = PHY_DRV_ODT_40;
202 tsel_wr_select_n = PHY_DRV_ODT_40;
203
204 tsel_idle_select_p = PHY_DRV_ODT_Hi_Z;
205 tsel_idle_select_n = PHY_DRV_ODT_240;
206
207 ca_tsel_wr_select_p = PHY_DRV_ODT_40;
208 ca_tsel_wr_select_n = PHY_DRV_ODT_40;
209 } else if (params->dramtype == LPDDR3) {
210 tsel_rd_select_p = PHY_DRV_ODT_240;
211 tsel_rd_select_n = PHY_DRV_ODT_Hi_Z;
212
213 tsel_wr_select_p = PHY_DRV_ODT_34_3;
214 tsel_wr_select_n = PHY_DRV_ODT_34_3;
215
216 tsel_idle_select_p = PHY_DRV_ODT_240;
217 tsel_idle_select_n = PHY_DRV_ODT_Hi_Z;
218
219 ca_tsel_wr_select_p = PHY_DRV_ODT_48;
220 ca_tsel_wr_select_n = PHY_DRV_ODT_48;
221 } else {
222 tsel_rd_select_p = PHY_DRV_ODT_240;
223 tsel_rd_select_n = PHY_DRV_ODT_240;
224
225 tsel_wr_select_p = PHY_DRV_ODT_34_3;
226 tsel_wr_select_n = PHY_DRV_ODT_34_3;
227
228 tsel_idle_select_p = PHY_DRV_ODT_240;
229 tsel_idle_select_n = PHY_DRV_ODT_240;
230
231 ca_tsel_wr_select_p = PHY_DRV_ODT_34_3;
232 ca_tsel_wr_select_n = PHY_DRV_ODT_34_3;
233 }
234
235 if (params->odt == 1)
236 tsel_rd_en = 1;
237 else
238 tsel_rd_en = 0;
239
240 tsel_wr_en = 0;
241 tsel_idle_en = 0;
242
243 /*
244 * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
245 * sets termination values for read/idle cycles and drive strength
246 * for write cycles for DQ/DM
247 */
248 reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
249 (tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) |
250 (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
251 clrsetbits32(&denali_phy[6], 0xffffff, reg_value);
252 clrsetbits32(&denali_phy[134], 0xffffff, reg_value);
253 clrsetbits32(&denali_phy[262], 0xffffff, reg_value);
254 clrsetbits32(&denali_phy[390], 0xffffff, reg_value);
255
256 /*
257 * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0
258 * sets termination values for read/idle cycles and drive strength
259 * for write cycles for DQS
260 */
261 clrsetbits32(&denali_phy[7], 0xffffff, reg_value);
262 clrsetbits32(&denali_phy[135], 0xffffff, reg_value);
263 clrsetbits32(&denali_phy[263], 0xffffff, reg_value);
264 clrsetbits32(&denali_phy[391], 0xffffff, reg_value);
265
266 /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
267 reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4);
268 clrsetbits32(&denali_phy[544], 0xff, reg_value);
269 clrsetbits32(&denali_phy[672], 0xff, reg_value);
270 clrsetbits32(&denali_phy[800], 0xff, reg_value);
271
272 /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
273 clrsetbits32(&denali_phy[928], 0xff, reg_value);
274
275 /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
276 clrsetbits32(&denali_phy[937], 0xff, reg_value);
277
278 /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
279 clrsetbits32(&denali_phy[935], 0xff, reg_value);
280
281 /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
282 clrsetbits32(&denali_phy[939], 0xff, reg_value);
283
284 /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
285 clrsetbits32(&denali_phy[929], 0xff, reg_value);
286
287 /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
288 clrsetbits32(&denali_phy[924], 0xff,
289 tsel_wr_select_n | (tsel_wr_select_p << 4));
290 clrsetbits32(&denali_phy[925], 0xff,
291 tsel_rd_select_n | (tsel_rd_select_p << 4));
292
293 /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */
294 reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
295 << 16;
296 clrsetbits32(&denali_phy[5], 0x7 << 16, reg_value);
297 clrsetbits32(&denali_phy[133], 0x7 << 16, reg_value);
298 clrsetbits32(&denali_phy[261], 0x7 << 16, reg_value);
299 clrsetbits32(&denali_phy[389], 0x7 << 16, reg_value);
300
301 /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */
302 reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
303 << 24;
304 clrsetbits32(&denali_phy[6], 0x7 << 24, reg_value);
305 clrsetbits32(&denali_phy[134], 0x7 << 24, reg_value);
306 clrsetbits32(&denali_phy[262], 0x7 << 24, reg_value);
307 clrsetbits32(&denali_phy[390], 0x7 << 24, reg_value);
308
309 /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */
310 reg_value = tsel_wr_en << 8;
311 clrsetbits32(&denali_phy[518], 0x1 << 8, reg_value);
312 clrsetbits32(&denali_phy[646], 0x1 << 8, reg_value);
313 clrsetbits32(&denali_phy[774], 0x1 << 8, reg_value);
314
315 /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */
316 reg_value = tsel_wr_en << 17;
317 clrsetbits32(&denali_phy[933], 0x1 << 17, reg_value);
318 /*
319 * pad_rst/cke/cs/clk_term tsel 1bits
320 * DENALI_PHY_938/936/940/934 offset_17
321 */
322 clrsetbits32(&denali_phy[938], 0x1 << 17, reg_value);
323 clrsetbits32(&denali_phy[936], 0x1 << 17, reg_value);
324 clrsetbits32(&denali_phy[940], 0x1 << 17, reg_value);
325 clrsetbits32(&denali_phy[934], 0x1 << 17, reg_value);
326
327 /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
328 clrsetbits32(&denali_phy[930], 0x1 << 17, reg_value);
329 }
330
331 static void phy_io_config(u32 channel, const struct rk3399_sdram_params *params)
332 {
333 u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
334 u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
335 u32 mode_sel = 0;
336 u32 reg_value;
337 u32 drv_value, odt_value;
338 u32 speed;
339
340 /* vref setting */
341 if (params->dramtype == LPDDR4) {
342 /* LPDDR4 */
343 vref_mode_dq = 0x6;
344 vref_value_dq = 0x1f;
345 vref_mode_ac = 0x6;
346 vref_value_ac = 0x1f;
347 } else if (params->dramtype == LPDDR3) {
348 if (params->odt == 1) {
349 vref_mode_dq = 0x5; /* LPDDR3 ODT */
350 drv_value = (read32(&denali_phy[6]) >> 12) & 0xf;
351 odt_value = (read32(&denali_phy[6]) >> 4) & 0xf;
352 if (drv_value == PHY_DRV_ODT_48) {
353 switch (odt_value) {
354 case PHY_DRV_ODT_240:
355 vref_value_dq = 0x16;
356 break;
357 case PHY_DRV_ODT_120:
358 vref_value_dq = 0x26;
359 break;
360 case PHY_DRV_ODT_60:
361 vref_value_dq = 0x36;
362 break;
363 default:
364 die("Halting: Invalid ODT value.\n");
365 }
366 } else if (drv_value == PHY_DRV_ODT_40) {
367 switch (odt_value) {
368 case PHY_DRV_ODT_240:
369 vref_value_dq = 0x19;
370 break;
371 case PHY_DRV_ODT_120:
372 vref_value_dq = 0x23;
373 break;
374 case PHY_DRV_ODT_60:
375 vref_value_dq = 0x31;
376 break;
377 default:
378 die("Halting: Invalid ODT value.\n");
379 }
380 } else if (drv_value == PHY_DRV_ODT_34_3) {
381 switch (odt_value) {
382 case PHY_DRV_ODT_240:
383 vref_value_dq = 0x17;
384 break;
385 case PHY_DRV_ODT_120:
386 vref_value_dq = 0x20;
387 break;
388 case PHY_DRV_ODT_60:
389 vref_value_dq = 0x2e;
390 break;
391 default:
392 die("Halting: Invalid ODT value.\n");
393 }
394 } else {
395 die("Halting: Invalid DRV value.\n");
396 }
397 } else {
398 vref_mode_dq = 0x2; /* LPDDR3 */
399 vref_value_dq = 0x1f;
400 }
401 vref_mode_ac = 0x2;
402 vref_value_ac = 0x1f;
403 } else if (params->dramtype == DDR3) {
404 /* DDR3L */
405 vref_mode_dq = 0x1;
406 vref_value_dq = 0x1f;
407 vref_mode_ac = 0x1;
408 vref_value_ac = 0x1f;
409 } else {
410 die("Halting: Unknown DRAM type.\n");
411 }
412
413 reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
414
415 /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
416 clrsetbits32(&denali_phy[913], 0xfff << 8, reg_value << 8);
417 /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
418 clrsetbits32(&denali_phy[914], 0xfff, reg_value);
419 /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
420 clrsetbits32(&denali_phy[914], 0xfff << 16, reg_value << 16);
421 /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
422 clrsetbits32(&denali_phy[915], 0xfff, reg_value);
423
424 reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
425
426 /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
427 clrsetbits32(&denali_phy[915], 0xfff << 16, reg_value << 16);
428
429 if (params->dramtype == LPDDR4)
430 mode_sel = 0x6;
431 else if (params->dramtype == LPDDR3)
432 mode_sel = 0x0;
433 else if (params->dramtype == DDR3)
434 mode_sel = 0x1;
435
436 /* PHY_924 PHY_PAD_FDBK_DRIVE */
437 clrsetbits32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
438 /* PHY_926 PHY_PAD_DATA_DRIVE */
439 clrsetbits32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
440 /* PHY_927 PHY_PAD_DQS_DRIVE */
441 clrsetbits32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
442 /* PHY_928 PHY_PAD_ADDR_DRIVE */
443 clrsetbits32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
444 /* PHY_929 PHY_PAD_CLK_DRIVE */
445 clrsetbits32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
446 /* PHY_935 PHY_PAD_CKE_DRIVE */
447 clrsetbits32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
448 /* PHY_937 PHY_PAD_RST_DRIVE */
449 clrsetbits32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
450 /* PHY_939 PHY_PAD_CS_DRIVE */
451 clrsetbits32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
452
453 /* speed setting */
454 if (params->ddr_freq < 400 * MHz)
455 speed = 0x0;
456 else if (params->ddr_freq < 800 * MHz)
457 speed = 0x1;
458 else if (params->ddr_freq < 1200 * MHz)
459 speed = 0x2;
460 else
461 speed = 0x3;
462
463 /* PHY_924 PHY_PAD_FDBK_DRIVE */
464 clrsetbits32(&denali_phy[924], 0x3 << 21, speed << 21);
465 /* PHY_926 PHY_PAD_DATA_DRIVE */
466 clrsetbits32(&denali_phy[926], 0x3 << 9, speed << 9);
467 /* PHY_927 PHY_PAD_DQS_DRIVE */
468 clrsetbits32(&denali_phy[927], 0x3 << 9, speed << 9);
469 /* PHY_928 PHY_PAD_ADDR_DRIVE */
470 clrsetbits32(&denali_phy[928], 0x3 << 17, speed << 17);
471 /* PHY_929 PHY_PAD_CLK_DRIVE */
472 clrsetbits32(&denali_phy[929], 0x3 << 17, speed << 17);
473 /* PHY_935 PHY_PAD_CKE_DRIVE */
474 clrsetbits32(&denali_phy[935], 0x3 << 17, speed << 17);
475 /* PHY_937 PHY_PAD_RST_DRIVE */
476 clrsetbits32(&denali_phy[937], 0x3 << 17, speed << 17);
477 /* PHY_939 PHY_PAD_CS_DRIVE */
478 clrsetbits32(&denali_phy[939], 0x3 << 17, speed << 17);
479 }
480
481 static int pctl_cfg(u32 channel, const struct rk3399_sdram_params *params)
482 {
483 u32 *denali_ctl = rk3399_ddr_pctl[channel]->denali_ctl;
484 u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi;
485 u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
486 const u32 *params_ctl = params->pctl_regs.denali_ctl;
487 const u32 *params_phy = params->phy_regs.denali_phy;
488 u32 tmp, tmp1, tmp2;
489 u32 pwrup_srefresh_exit;
490 struct stopwatch sw;
491
492 /*
493 * work around controller bug:
494 * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
495 */
496 copy_to_reg(&denali_ctl[1], &params_ctl[1],
497 sizeof(struct rk3399_ddr_pctl_regs) - 4);
498 write32(&denali_ctl[0], params_ctl[0]);
499 copy_to_reg(denali_pi, &params->pi_regs.denali_pi[0],
500 sizeof(struct rk3399_ddr_pi_regs));
501 /* rank count need to set for init */
502 set_memory_map(channel, params);
503
504 write32(&denali_phy[910], params->phy_regs.denali_phy[910]);
505 write32(&denali_phy[911], params->phy_regs.denali_phy[911]);
506 write32(&denali_phy[912], params->phy_regs.denali_phy[912]);
507
508 pwrup_srefresh_exit = read32(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT;
509 clrbits32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
510
511 /* PHY_DLL_RST_EN */
512 clrsetbits32(&denali_phy[957], 0x3 << 24, 1 << 24);
513
514 setbits32(&denali_pi[0], START);
515 setbits32(&denali_ctl[0], START);
516
517 while (1) {
518 tmp = read32(&denali_phy[920]);
519 tmp1 = read32(&denali_phy[921]);
520 tmp2 = read32(&denali_phy[922]);
521 if ((((tmp >> 16) & 0x1) == 0x1) &&
522 (((tmp1 >> 16) & 0x1) == 0x1) &&
523 (((tmp1 >> 0) & 0x1) == 0x1) &&
524 (((tmp2 >> 0) & 0x1) == 0x1))
525 break;
526 }
527
528 copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);
529 copy_to_reg(&denali_phy[0], &params_phy[0], (90 - 0 + 1) * 4);
530 copy_to_reg(&denali_phy[128], &params_phy[128], (218 - 128 + 1) * 4);
531 copy_to_reg(&denali_phy[256], &params_phy[256], (346 - 256 + 1) * 4);
532 copy_to_reg(&denali_phy[384], &params_phy[384], (474 - 384 + 1) * 4);
533 copy_to_reg(&denali_phy[512], &params_phy[512], (549 - 512 + 1) * 4);
534 copy_to_reg(&denali_phy[640], &params_phy[640], (677 - 640 + 1) * 4);
535 copy_to_reg(&denali_phy[768], &params_phy[768], (805 - 768 + 1) * 4);
536 set_ds_odt(channel, params);
537
538 /*
539 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
540 * dqs_tsel_wr_end[7:4] add Half cycle
541 */
542 tmp = (read32(&denali_phy[84]) >> 8) & 0xff;
543 clrsetbits32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8);
544 tmp = (read32(&denali_phy[212]) >> 8) & 0xff;
545 clrsetbits32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8);
546 tmp = (read32(&denali_phy[340]) >> 8) & 0xff;
547 clrsetbits32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8);
548 tmp = (read32(&denali_phy[468]) >> 8) & 0xff;
549 clrsetbits32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8);
550
551 /*
552 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
553 * dq_tsel_wr_end[7:4] add Half cycle
554 */
555 tmp = (read32(&denali_phy[83]) >> 16) & 0xff;
556 clrsetbits32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16);
557 tmp = (read32(&denali_phy[211]) >> 16) & 0xff;
558 clrsetbits32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16);
559 tmp = (read32(&denali_phy[339]) >> 16) & 0xff;
560 clrsetbits32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16);
561 tmp = (read32(&denali_phy[467]) >> 16) & 0xff;
562 clrsetbits32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
563
564 phy_io_config(channel, params);
565
566 /* PHY_DLL_RST_EN */
567 clrsetbits32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
568
569 /* FIXME: need to care ERROR bit */
570 stopwatch_init_msecs_expire(&sw, 100);
571 while (!(read32(&denali_ctl[203]) & (1 << 3))) {
572 if (stopwatch_expired(&sw))
573 return -1;
574 }
575
576 clrsetbits32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
577 pwrup_srefresh_exit);
578 return 0;
579 }
580
581 static void select_per_cs_training_index(u32 channel, u32 rank)
582 {
583 u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
584
585 /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
586 if ((read32(&denali_phy[84])>>16) & 1) {
587 /*
588 * PHY_8/136/264/392
589 * phy_per_cs_training_index_X 1bit offset_24
590 */
591 clrsetbits32(&denali_phy[8], 0x1 << 24, rank << 24);
592 clrsetbits32(&denali_phy[136], 0x1 << 24, rank << 24);
593 clrsetbits32(&denali_phy[264], 0x1 << 24, rank << 24);
594 clrsetbits32(&denali_phy[392], 0x1 << 24, rank << 24);
595 }
596 }
597
598 static void override_write_leveling_value(u32 channel)
599 {
600 u32 *denali_ctl = rk3399_ddr_pctl[channel]->denali_ctl;
601 u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
602 u32 byte;
603
604 /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
605 setbits32(&denali_phy[896], 1);
606
607 /*
608 * PHY_8/136/264/392
609 * phy_per_cs_training_multicast_en_X 1bit offset_16
610 */
611 clrsetbits32(&denali_phy[8], 0x1 << 16, 1 << 16);
612 clrsetbits32(&denali_phy[136], 0x1 << 16, 1 << 16);
613 clrsetbits32(&denali_phy[264], 0x1 << 16, 1 << 16);
614 clrsetbits32(&denali_phy[392], 0x1 << 16, 1 << 16);
615
616 for (byte = 0; byte < 4; byte++)
617 clrsetbits32(&denali_phy[63 + (128 * byte)], 0xffff << 16,
618 0x200 << 16);
619
620 /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
621 clrbits32(&denali_phy[896], 1);
622
623 /* CTL_200 ctrlupd_req 1bit offset_8 */
624 clrsetbits32(&denali_ctl[200], 0x1 << 8, 0x1 << 8);
625 }
626
627 static u32 get_rank_mask(u32 channel, const struct rk3399_sdram_params *params)
628 {
629 const u32 rank = params->ch[channel].rank;
630
631 /* required rank mask is different for LPDDR4 */
632 if (params->dramtype == LPDDR4)
633 return (rank == 1) ? 0x5 : 0xf;
634 else
635 return (rank == 1) ? 0x1 : 0x3;
636 }
637
638 static int data_training_ca(u32 channel, const struct rk3399_sdram_params *params)
639 {
640 u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi;
641 u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
642 u32 obs_0, obs_1, obs_2;
643 const u32 rank_mask = get_rank_mask(channel, params);
644 u32 i, tmp;
645
646 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
647 write32(&denali_pi[175], 0x00003f7c);
648
649 for (i = 0; i < MAX_RANKS_PER_CHANNEL; i++) {
650 if (!(rank_mask & (1 << i)))
651 continue;
652
653 select_per_cs_training_index(channel, i);
654 /* PI_100 PI_CALVL_EN:RW:8:2 */
655 clrsetbits32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
656 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
657 clrsetbits32(&denali_pi[92], (0x1 << 16) | (0x3 << 24),
658 (0x1 << 16) | (i << 24));
659
660 while (1) {
661 /* PI_174 PI_INT_STATUS:RD:8:18 */
662 tmp = read32(&denali_pi[174]) >> 8;
663
664 /*
665 * check status obs
666 * PHY_532/660/789 phy_adr_calvl_obs1_:0:32
667 */
668 obs_0 = read32(&denali_phy[532]);
669 obs_1 = read32(&denali_phy[660]);
670 obs_2 = read32(&denali_phy[788]);
671 if (((obs_0 >> 30) & 0x3) ||
672 ((obs_1 >> 30) & 0x3) ||
673 ((obs_2 >> 30) & 0x3))
674 return -1;
675 if ((((tmp >> 11) & 0x1) == 0x1) &&
676 (((tmp >> 13) & 0x1) == 0x1) &&
677 (((tmp >> 5) & 0x1) == 0x0))
678 break;
679 else if (((tmp >> 5) & 0x1) == 0x1)
680 return -1;
681 }
682 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
683 write32(&denali_pi[175], 0x00003f7c);
684 }
685 clrbits32(&denali_pi[100], 0x3 << 8);
686
687 return 0;
688 }
689
690 static int data_training_wl(u32 channel, const struct rk3399_sdram_params *params)
691 {
692 u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi;
693 u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
694 u32 obs_0, obs_1, obs_2, obs_3;
695 u32 rank = params->ch[channel].rank;
696 u32 i, tmp;
697
698 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
699 write32(&denali_pi[175], 0x00003f7c);
700
701 for (i = 0; i < rank; i++) {
702 select_per_cs_training_index(channel, i);
703 /* PI_60 PI_WRLVL_EN:RW:8:2 */
704 clrsetbits32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
705 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
706 clrsetbits32(&denali_pi[59], (0x1 << 8) | (0x3 << 16), (0x1 << 8) | (i << 16));
707
708 while (1) {
709 /* PI_174 PI_INT_STATUS:RD:8:18 */
710 tmp = read32(&denali_pi[174]) >> 8;
711
712 /*
713 * check status obs, if error maybe can not
714 * get leveling done PHY_40/168/296/424
715 * phy_wrlvl_status_obs_X:0:13
716 */
717 obs_0 = read32(&denali_phy[40]);
718 obs_1 = read32(&denali_phy[168]);
719 obs_2 = read32(&denali_phy[296]);
720 obs_3 = read32(&denali_phy[424]);
721 if (((obs_0 >> 12) & 0x1) ||
722 ((obs_1 >> 12) & 0x1) ||
723 ((obs_2 >> 12) & 0x1) ||
724 ((obs_3 >> 12) & 0x1))
725 return -1;
726 if ((((tmp >> 10) & 0x1) == 0x1) &&
727 (((tmp >> 13) & 0x1) == 0x1) &&
728 (((tmp >> 4) & 0x1) == 0x0))
729 break;
730 else if (((tmp >> 4) & 0x1) == 0x1)
731 return -1;
732 }
733 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
734 write32(&denali_pi[175], 0x00003f7c);
735 }
736
737 override_write_leveling_value(channel);
738 clrbits32(&denali_pi[60], 0x3 << 8);
739
740 return 0;
741 }
742
743 static int data_training_rg(u32 channel, const struct rk3399_sdram_params *params)
744 {
745 u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi;
746 u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
747 u32 rank = params->ch[channel].rank;
748 u32 obs_0, obs_1, obs_2, obs_3;
749 u32 reg_value = 0;
750 u32 i, tmp;
751
752 /*
753 * The differential signal of DQS needs to keep low level
754 * before gate training. RPULL will connect 4Kn from PADP
755 * to VSS and a 4Kn from PADN to VDDQ to ensure it.
756 * But if it has PHY side ODT connect at this time,
757 * it will change the DQS signal level. So disable PHY
758 * side ODT before gate training and restore ODT state
759 * after gate training.
760 */
761 if (params->dramtype != LPDDR4) {
762 reg_value = (read32(&denali_phy[6]) >> 24) & 0x7;
763
764 /*
765 * phy_dqs_tsel_enable_X 3bits
766 * DENALI_PHY_6/134/262/390 offset_24
767 */
768 clrbits32(&denali_phy[6], 0x7 << 24);
769 clrbits32(&denali_phy[134], 0x7 << 24);
770 clrbits32(&denali_phy[262], 0x7 << 24);
771 clrbits32(&denali_phy[390], 0x7 << 24);
772 }
773
774 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
775 write32(&denali_pi[175], 0x00003f7c);
776
777 for (i = 0; i < rank; i++) {
778 select_per_cs_training_index(channel, i);
779 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
780 clrsetbits32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
781 /*
782 * PI_74 PI_RDLVL_GATE_REQ:WR:16:1
783 * PI_RDLVL_CS:RW:24:2
784 */
785 clrsetbits32(&denali_pi[74], (0x1 << 16) | (0x3 << 24),
786 (0x1 << 16) | (i << 24));
787
788 while (1) {
789 /* PI_174 PI_INT_STATUS:RD:8:18 */
790 tmp = read32(&denali_pi[174]) >> 8;
791
792 /*
793 * check status obs
794 * PHY_43/171/299/427
795 * PHY_GTLVL_STATUS_OBS_x:16:8
796 */
797 obs_0 = read32(&denali_phy[43]);
798 obs_1 = read32(&denali_phy[171]);
799 obs_2 = read32(&denali_phy[299]);
800 obs_3 = read32(&denali_phy[427]);
801 if (((obs_0 >> (16 + 6)) & 0x3) ||
802 ((obs_1 >> (16 + 6)) & 0x3) ||
803 ((obs_2 >> (16 + 6)) & 0x3) ||
804 ((obs_3 >> (16 + 6)) & 0x3))
805 return -1;
806 if ((((tmp >> 9) & 0x1) == 0x1) &&
807 (((tmp >> 13) & 0x1) == 0x1) &&
808 (((tmp >> 3) & 0x1) == 0x0))
809 break;
810 else if (((tmp >> 3) & 0x1) == 0x1)
811 return -1;
812 }
813 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
814 write32(&denali_pi[175], 0x00003f7c);
815 }
816 clrbits32(&denali_pi[80], 0x3 << 24);
817
818 if (params->dramtype != LPDDR4) {
819 /*
820 * phy_dqs_tsel_enable_X 3bits
821 * DENALI_PHY_6/134/262/390 offset_24
822 */
823 tmp = reg_value << 24;
824 clrsetbits32(&denali_phy[6], 0x7 << 24, tmp);
825 clrsetbits32(&denali_phy[134], 0x7 << 24, tmp);
826 clrsetbits32(&denali_phy[262], 0x7 << 24, tmp);
827 clrsetbits32(&denali_phy[390], 0x7 << 24, tmp);
828 }
829 return 0;
830 }
831
832 static int data_training_rl(u32 channel, const struct rk3399_sdram_params *params)
833 {
834 u32 rank = params->ch[channel].rank;
835 u32 i, tmp;
836
837 u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi;
838
839 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
840 write32(&denali_pi[175], 0x00003f7c);
841
842 for (i = 0; i < rank; i++) {
843 select_per_cs_training_index(channel, i);
844 /* PI_80 PI_RDLVL_EN:RW:16:2 */
845 clrsetbits32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
846 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
847 clrsetbits32(&denali_pi[74], (0x1 << 8) | (0x3 << 24), (0x1 << 8) | (i << 24));
848
849 while (1) {
850 /* PI_174 PI_INT_STATUS:RD:8:18 */
851 tmp = read32(&denali_pi[174]) >> 8;
852
853 /*
854 * make sure status obs not report error bit
855 * PHY_46/174/302/430
856 * phy_rdlvl_status_obs_X:16:8
857 */
858 if ((((tmp >> 8) & 0x1) == 0x1) && (((tmp >> 13) & 0x1) == 0x1)
859 && (((tmp >> 2) & 0x1) == 0x0))
860 break;
861 else if (((tmp >> 2) & 0x1) == 0x1)
862 return -1;
863 }
864 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
865 write32(&denali_pi[175], 0x00003f7c);
866 }
867 clrbits32(&denali_pi[80], 0x3 << 16);
868
869 return 0;
870 }
871
872 static int data_training_wdql(u32 channel, const struct rk3399_sdram_params *params)
873 {
874 u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi;
875 const u32 rank_mask = get_rank_mask(channel, params);
876 u32 i, tmp;
877
878 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
879 write32(&denali_pi[175], 0x00003f7c);
880
881 for (i = 0; i < MAX_RANKS_PER_CHANNEL; i++) {
882 if (!(rank_mask & (1 << i)))
883 continue;
884
885 select_per_cs_training_index(channel, i);
886 /*
887 * disable PI_WDQLVL_VREF_EN before wdq leveling?
888 * PI_181 PI_WDQLVL_VREF_EN:RW:8:1
889 */
890 clrbits32(&denali_pi[181], 0x1 << 8);
891 /* PI_124 PI_WDQLVL_EN:RW:16:2 */
892 clrsetbits32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
893 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
894 clrsetbits32(&denali_pi[121], (0x1 << 8) | (0x3 << 16), (0x1 << 8) | (i << 16));
895
896 while (1) {
897 /* PI_174 PI_INT_STATUS:RD:8:18 */
898 tmp = read32(&denali_pi[174]) >> 8;
899 if ((((tmp >> 12) & 0x1) == 0x1) && (((tmp >> 13) & 0x1) == 0x1)
900 && (((tmp >> 6) & 0x1) == 0x0))
901 break;
902 else if (((tmp >> 6) & 0x1) == 0x1)
903 return -1;
904 }
905 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
906 write32(&denali_pi[175], 0x00003f7c);
907 }
908 clrbits32(&denali_pi[124], 0x3 << 16);
909
910 return 0;
911 }
912
913
914 static int data_training(u32 channel, const struct rk3399_sdram_params *params,
915 u32 training_flag)
916 {
917 u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
918 int ret;
919
920 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
921 setbits32(&denali_phy[927], (1 << 22));
922
923 if (training_flag == PI_FULL_TRAINING) {
924 if (params->dramtype == LPDDR4) {
925 training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
926 PI_READ_GATE_TRAINING |
927 PI_READ_LEVELING | PI_WDQ_LEVELING;
928 } else if (params->dramtype == LPDDR3) {
929 training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
930 PI_READ_GATE_TRAINING;
931 } else if (params->dramtype == DDR3) {
932 training_flag = PI_WRITE_LEVELING |
933 PI_READ_GATE_TRAINING |
934 PI_READ_LEVELING;
935 }
936 }
937
938 /* ca training(LPDDR4,LPDDR3 support) */
939 if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) {
940 ret = data_training_ca(channel, params);
941 if (ret) {
942 printk(BIOS_ERR, "Channel %d CA training failed\n", channel);
943 return ret;
944 }
945 }
946
947 /* write leveling(LPDDR4,LPDDR3,DDR3 support) */
948 if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) {
949 ret = data_training_wl(channel, params);
950 if (ret) {
951 printk(BIOS_ERR, "Channel %d WL training failed\n", channel);
952 return ret;
953 }
954 }
955
956 /* read gate training(LPDDR4,LPDDR3,DDR3 support) */
957 if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
958 ret = data_training_rg(channel, params);
959 if (ret) {
960 printk(BIOS_ERR, "Channel %d RG training failed\n", channel);
961 return ret;
962 }
963 }
964
965 /* read leveling(LPDDR4,LPDDR3,DDR3 support) */
966 if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {
967 ret = data_training_rl(channel, params);
968 if (ret) {
969 printk(BIOS_ERR, "Channel %d RL training failed\n", channel);
970 return ret;
971 }
972 }
973
974 /* wdq leveling(LPDDR4 support) */
975 if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
976 ret = data_training_wdql(channel, params);
977 if (ret) {
978 printk(BIOS_ERR, "Channel %d WDQL training failed\n", channel);
979 return ret;
980 }
981 }
982
983 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
984 clrbits32(&denali_phy[927], (1 << 22));
985
986 return 0;
987 }
988
989 static void set_ddrconfig(const struct rk3399_sdram_params *params,
990 unsigned char channel, u32 ddrconfig)
991 {
992 /* only need to set ddrconfig */
993 struct rk3399_msch_regs *ddr_msch_regs = rk3399_msch[channel];
994 unsigned int cs0_cap = 0;
995 unsigned int cs1_cap = 0;
996
997 cs0_cap = (1 << (params->ch[channel].cs0_row
998 + params->ch[channel].col
999 + params->ch[channel].bk
1000 + params->ch[channel].bw - 20));
1001 if (params->ch[channel].rank > 1)
1002 cs1_cap = cs0_cap >> (params->ch[channel].cs0_row
1003 - params->ch[channel].cs1_row);
1004 if (params->ch[channel].row_3_4) {
1005 cs0_cap = cs0_cap * 3 / 4;
1006 cs1_cap = cs1_cap * 3 / 4;
1007 }
1008
1009 write32(&ddr_msch_regs->ddrconf, ddrconfig | (ddrconfig << 8));
1010 write32(&ddr_msch_regs->ddrsize, ((cs0_cap / 32) & 0xff) |
1011 (((cs1_cap / 32) & 0xff) << 8));
1012 }
1013
1014 static void dram_all_config(const struct rk3399_sdram_params *params)
1015 {
1016 u32 sys_reg = 0;
1017 unsigned int channel;
1018 unsigned int use;
1019
1020 sys_reg |= SYS_REG_ENC_DDRTYPE(params->dramtype);
1021 sys_reg |= SYS_REG_ENC_NUM_CH(params->num_channels);
1022 for (channel = 0, use = 0; (use < params->num_channels) && (channel < 2); channel++) {
1023 const struct rk3399_sdram_channel *info = &params->ch[channel];
1024 struct rk3399_msch_regs *ddr_msch_regs;
1025 const struct rk3399_msch_timings *noc_timing;
1026
1027 if (params->ch[channel].col == 0)
1028 continue;
1029 use++;
1030 sys_reg |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel);
1031 sys_reg |= SYS_REG_ENC_CHINFO(channel);
1032 sys_reg |= SYS_REG_ENC_RANK(info->rank, channel);
1033 sys_reg |= SYS_REG_ENC_COL(info->col, channel);
1034 sys_reg |= SYS_REG_ENC_BK(info->bk, channel);
1035 sys_reg |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel);
1036 if (params->ch[channel].rank > 1)
1037 sys_reg |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel);
1038 sys_reg |= SYS_REG_ENC_BW(info->bw, channel);
1039 sys_reg |= SYS_REG_ENC_DBW(info->dbw, channel);
1040
1041 ddr_msch_regs = rk3399_msch[channel];
1042 noc_timing = &params->ch[channel].noc_timings;
1043 write32(&ddr_msch_regs->ddrtiminga0.d32,
1044 noc_timing->ddrtiminga0.d32);
1045 write32(&ddr_msch_regs->ddrtimingb0.d32,
1046 noc_timing->ddrtimingb0.d32);
1047 write32(&ddr_msch_regs->ddrtimingc0.d32,
1048 noc_timing->ddrtimingc0.d32);
1049 write32(&ddr_msch_regs->devtodev0.d32,
1050 noc_timing->devtodev0.d32);
1051 write32(&ddr_msch_regs->ddrmode.d32,
1052 noc_timing->ddrmode.d32);
1053
1054 /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
1055 if (params->ch[channel].rank == 1)
1056 setbits32(&rk3399_ddr_pctl[channel]->denali_ctl[276],
1057 1 << 17);
1058 }
1059
1060 write32(&rk3399_pmugrf->os_reg2, sys_reg);
1061 DDR_STRIDE(params->stride);
1062
1063 /* reboot hold register set */
1064 write32(&pmucru_ptr->pmucru_rstnhold_con[1],
1065 PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) |
1066 PRESET_GPIO1_HOLD(1));
1067 clrsetbits32(&cru_ptr->glb_rst_con, 0x3, 0x3);
1068 }
1069
1070 static void switch_to_phy_index1(const struct rk3399_sdram_params *params)
1071 {
1072 u32 channel;
1073 u32 *denali_phy;
1074 struct stopwatch sw;
1075 u32 ch_count = params->num_channels;
1076
1077 stopwatch_init_msecs_expire(&sw, 100);
1078 write32(&rk3399_ddr_cic->cic_ctrl0,
1079 RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1,
1080 1 << 4 | 1 << 2 | 1));
1081 while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 2))) {
1082 if (stopwatch_expired(&sw)) {
1083 printk(BIOS_ERR,
1084 "index1 frequency change overtime, reset\n");
1085 board_reset();
1086 }
1087 }
1088
1089 stopwatch_init_msecs_expire(&sw, 100);
1090 write32(&rk3399_ddr_cic->cic_ctrl0, RK_CLRSETBITS(1 << 1, 1 << 1));
1091 while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 0))) {
1092 if (stopwatch_expired(&sw)) {
1093 printk(BIOS_ERR,
1094 "index1 frequency done overtime, reset\n");
1095 board_reset();
1096 }
1097 }
1098
1099 for (channel = 0; channel < ch_count; channel++) {
1100 denali_phy = rk3399_ddr_publ[channel]->denali_phy;
1101 clrsetbits32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
1102 if (data_training(channel, params, PI_FULL_TRAINING)) {
1103 printk(BIOS_ERR, "index1 training failed, reset\n");
1104 board_reset();
1105 }
1106 }
1107 }
1108
1109 void sdram_init(const struct rk3399_sdram_params *params)
1110 {
1111 unsigned char dramtype = params->dramtype;
1112 unsigned int ddr_freq = params->ddr_freq;
1113 int channel;
1114
1115 printk(BIOS_INFO, "Starting SDRAM initialization...\n");
1116
1117 if ((dramtype == DDR3 && ddr_freq > 800*MHz) ||
1118 (dramtype == LPDDR3 && ddr_freq > 933*MHz) ||
1119 (dramtype == LPDDR4 && ddr_freq > 800*MHz))
1120 die("SDRAM frequency is to high!");
1121
1122 rkclk_configure_ddr(ddr_freq);
1123
1124 for (channel = 0; channel < 2; channel++) {
1125 phy_pctrl_reset(channel);
1126 phy_dll_bypass_set(rk3399_ddr_publ[channel], ddr_freq);
1127
1128 if (channel >= params->num_channels)
1129 continue;
1130
1131 /*
1132 * TODO: we need to find the root cause why this
1133 * step may fail, before that, we just reset the
1134 * system, and start again.
1135 */
1136 if (pctl_cfg(channel, params)) {
1137 printk(BIOS_ERR, "pctl_cfg fail, reset\n");
1138 board_reset();
1139 }
1140
1141 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
1142 if (dramtype == LPDDR3)
1143 udelay(10);
1144
1145 if (data_training(channel, params, PI_FULL_TRAINING)) {
1146 printk(BIOS_ERR, "SDRAM initialization failed, reset\n");
1147 board_reset();
1148 }
1149
1150 set_ddrconfig(params, channel, params->ch[channel].ddrconfig);
1151 }
1152 dram_all_config(params);
1153 switch_to_phy_index1(params);
1154
1155 printk(BIOS_INFO, "Finish SDRAM initialization...\n");
1156 }
1157
1158 size_t sdram_size_mb(void)
1159 {
1160 u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
1161 size_t chipsize_mb = 0;
1162 static size_t size_mb = 0;
1163 u32 ch;
1164
1165 if (!size_mb) {
1166 u32 sys_reg = read32(&rk3399_pmugrf->os_reg2);
1167 u32 ch_num = SYS_REG_DEC_NUM_CH(sys_reg);
1168
1169 for (ch = 0; ch < ch_num; ch++) {
1170 rank = SYS_REG_DEC_RANK(sys_reg, ch);
1171 col = SYS_REG_DEC_COL(sys_reg, ch);
1172 bk = SYS_REG_DEC_BK(sys_reg, ch);
1173 cs0_row = SYS_REG_DEC_CS0_ROW(sys_reg, ch);
1174 cs1_row = SYS_REG_DEC_CS1_ROW(sys_reg, ch);
1175 bw = SYS_REG_DEC_BW(sys_reg, ch);
1176 row_3_4 = SYS_REG_DEC_ROW_3_4(sys_reg, ch);
1177
1178 chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
1179
1180 if (rank > 1)
1181 chipsize_mb += chipsize_mb >>
1182 (cs0_row - cs1_row);
1183 if (row_3_4)
1184 chipsize_mb = chipsize_mb * 3 / 4;
1185 size_mb += chipsize_mb;
1186 }
1187
1188 /*
1189 * we use the 0x00000000~0xf7ffffff space
1190 * since 0xf8000000~0xffffffff is soc register space
1191 * so we reserve it
1192 */
1193 size_mb = MIN(size_mb, 0xf8000000/MiB);
1194 }
1195
1196 return size_mb;
1197 }
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