1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <console/console.h>
9 #include <soc/sysreg.h>
13 * Here is the rough outline of how we bring up the display:
14 * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD
15 * 2. Source determines video mode by reading DPCD receiver capability field
16 * (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD
18 * 3. Sink replies DPCD receiver capability field.
19 * 4. Source starts EDID read thru I2C-over-AUX.
20 * 5. Sink replies EDID thru I2C-over-AUX.
21 * 6. Source determines link configuration, such as MAX_LINK_RATE and
22 * MAX_LANE_COUNT. Source also determines which type of eDP Authentication
23 * method to use and writes DPCD link configuration field (DPCD 00100h to
24 * 0010Ah) including eDP configuration set (DPCD 0010Ah).
25 * 7. Source starts link training. Sink does clock recovery and equalization.
26 * 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh).
27 * 9. Sink replies DPCD link status field. If main link is not stable, Source
29 * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video
30 * parameters and recovers stream clock.
31 * 11. Source sends video data.
34 static int exynos_dp_init_dp(void)
39 /* SW defined function Normal operation */
40 exynos_dp_enable_sw_func(DP_ENABLE
);
42 ret
= exynos_dp_init_analog_func();
43 if (ret
!= EXYNOS_DP_SUCCESS
)
52 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data
)
55 unsigned char sum
= 0;
57 for (i
= 0; i
< EDID_BLOCK_LENGTH
; i
++)
58 sum
= sum
+ edid_data
[i
];
63 static unsigned int exynos_dp_read_edid(void)
65 unsigned char edid
[EDID_BLOCK_LENGTH
* 2];
66 unsigned int extend_block
= 0;
68 unsigned char test_vector
;
72 * EDID device address is 0x50.
73 * However, if necessary, you must have set upper address
74 * into E-EDID in I2C device, 0x30.
77 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
78 if (exynos_dp_read_byte_from_i2c
79 (I2C_EDID_DEVICE_ADDR
, EDID_EXTENSION_FLAG
, &extend_block
))
82 if (extend_block
> 0) {
84 retval
= exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR
,
87 &edid
[EDID_HEADER_PATTERN
]);
90 printk(BIOS_ERR
, "DP EDID Read failed!\n");
93 sum
= exynos_dp_calc_edid_check_sum(edid
);
95 printk(BIOS_ERR
, "DP EDID bad checksum!\n");
98 /* Read additional EDID data */
99 retval
= exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR
,
102 &edid
[EDID_BLOCK_LENGTH
]);
104 printk(BIOS_ERR
, "DP EDID Read failed!\n");
107 sum
= exynos_dp_calc_edid_check_sum(&edid
[EDID_BLOCK_LENGTH
]);
109 printk(BIOS_ERR
, "DP EDID bad checksum!\n");
112 exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST
,
114 if (test_vector
& DPCD_TEST_EDID_READ
) {
115 exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM
,
116 edid
[EDID_BLOCK_LENGTH
+ EDID_CHECKSUM
]);
117 exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE
,
118 DPCD_TEST_EDID_CHECKSUM_WRITE
);
122 retval
= exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR
,
125 &edid
[EDID_HEADER_PATTERN
]);
128 printk(BIOS_ERR
, "DP EDID Read failed!\n");
131 sum
= exynos_dp_calc_edid_check_sum(edid
);
133 printk(BIOS_ERR
, "DP EDID bad checksum!\n");
137 exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST
,
139 if (test_vector
& DPCD_TEST_EDID_READ
) {
140 exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM
,
141 edid
[EDID_CHECKSUM
]);
142 exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE
,
143 DPCD_TEST_EDID_CHECKSUM_WRITE
);
150 static unsigned int exynos_dp_handle_edid(struct edp_device_info
*edp_info
)
152 unsigned char buf
[12];
155 unsigned char retry_cnt
;
156 unsigned char dpcd_rev
[16];
157 unsigned char lane_bw
[16];
158 unsigned char lane_cnt
[16];
160 memset(dpcd_rev
, 0, sizeof(dpcd_rev
));
161 memset(lane_bw
, 0, sizeof(lane_bw
));
162 memset(lane_cnt
, 0, sizeof(lane_cnt
));
163 memset(buf
, 0, sizeof(buf
));
167 /* Read DPCD 0x0000-0x000b */
168 ret
= exynos_dp_read_bytes_from_dpcd(DPCD_DPCD_REV
, 12,
170 if (ret
!= EXYNOS_DP_SUCCESS
) {
171 if (retry_cnt
== 0) {
172 printk(BIOS_ERR
, "DP read_byte_from_dpcd() failed\n");
180 temp
= buf
[DPCD_DPCD_REV
];
181 if (temp
== DP_DPCD_REV_10
|| temp
== DP_DPCD_REV_11
)
182 edp_info
->dpcd_rev
= temp
;
184 printk(BIOS_ERR
, "DP Wrong DPCD Rev : %x\n", temp
);
187 temp
= buf
[DPCD_MAX_LINK_RATE
];
188 if (temp
== DP_LANE_BW_1_62
|| temp
== DP_LANE_BW_2_70
)
189 edp_info
->lane_bw
= temp
;
191 printk(BIOS_ERR
, "DP Wrong MAX LINK RATE : %x\n", temp
);
194 /*Refer VESA Display Port Standard Ver1.1a Page 120 */
195 if (edp_info
->dpcd_rev
== DP_DPCD_REV_11
) {
196 temp
= buf
[DPCD_MAX_LANE_COUNT
] & 0x1f;
197 if (buf
[DPCD_MAX_LANE_COUNT
] & 0x80)
198 edp_info
->dpcd_efc
= 1;
200 edp_info
->dpcd_efc
= 0;
202 temp
= buf
[DPCD_MAX_LANE_COUNT
];
203 edp_info
->dpcd_efc
= 0;
206 if (temp
== DP_LANE_CNT_1
|| temp
== DP_LANE_CNT_2
||
207 temp
== DP_LANE_CNT_4
) {
208 edp_info
->lane_cnt
= temp
;
210 printk(BIOS_ERR
, "DP Wrong MAX LANE COUNT : %x\n", temp
);
214 if (edp_info
->raw_edid
){
215 ret
= EXYNOS_DP_SUCCESS
;
216 printk(BIOS_SPEW
, "EDID compiled in, skipping read\n");
218 ret
= exynos_dp_read_edid();
219 if (ret
!= EXYNOS_DP_SUCCESS
) {
220 printk(BIOS_ERR
, "DP exynos_dp_read_edid() failed\n");
228 static void exynos_dp_init_training(void)
231 * MACRO_RST must be applied after the PLL_LOCK to avoid
232 * the DP inter pair skew issue for at least 10 us
234 exynos_dp_reset_macro();
236 /* All DP analog module power up */
237 exynos_dp_set_analog_power_down(POWER_ALL
, 0);
240 static unsigned int exynos_dp_link_start(struct edp_device_info
*edp_info
)
242 unsigned char buf
[5];
245 edp_info
->lt_info
.lt_status
= DP_LT_CR
;
246 edp_info
->lt_info
.ep_loop
= 0;
247 edp_info
->lt_info
.cr_loop
[0] = 0;
248 edp_info
->lt_info
.cr_loop
[1] = 0;
249 edp_info
->lt_info
.cr_loop
[2] = 0;
250 edp_info
->lt_info
.cr_loop
[3] = 0;
252 /* Set sink to D0 (Sink Not Ready) mode. */
253 ret
= exynos_dp_write_byte_to_dpcd(DPCD_SINK_POWER_STATE
,
254 DPCD_SET_POWER_STATE_D0
);
255 if (ret
!= EXYNOS_DP_SUCCESS
) {
256 printk(BIOS_ERR
, "DP write_dpcd_byte failed\n");
260 /* Set link rate and count as you want to establish*/
261 exynos_dp_set_link_bandwidth(edp_info
->lane_bw
);
262 exynos_dp_set_lane_count(edp_info
->lane_cnt
);
264 /* Setup RX configuration */
265 buf
[0] = edp_info
->lane_bw
;
266 buf
[1] = edp_info
->lane_cnt
;
268 ret
= exynos_dp_write_bytes_to_dpcd(DPCD_LINK_BW_SET
, 2,
270 if (ret
!= EXYNOS_DP_SUCCESS
) {
271 printk(BIOS_ERR
, "DP write_dpcd_byte failed\n");
275 exynos_dp_set_lane_pre_emphasis(PRE_EMPHASIS_LEVEL_0
,
278 /* Set training pattern 1 */
279 exynos_dp_set_training_pattern(TRAINING_PTN1
);
281 /* Set RX training pattern */
282 buf
[0] = DPCD_SCRAMBLING_DISABLED
| DPCD_TRAINING_PATTERN_1
;
284 buf
[1] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0
|
285 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0
;
286 buf
[2] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0
|
287 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0
;
288 buf
[3] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0
|
289 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0
;
290 buf
[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0
|
291 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0
;
293 ret
= exynos_dp_write_bytes_to_dpcd(DPCD_TRAINING_PATTERN_SET
,
295 if (ret
!= EXYNOS_DP_SUCCESS
) {
296 printk(BIOS_ERR
, "DP write_dpcd_byte failed\n");
302 static unsigned int exynos_dp_training_pattern_dis(void)
306 exynos_dp_set_training_pattern(DP_NONE
);
308 ret
= exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET
,
309 DPCD_TRAINING_PATTERN_DISABLED
);
310 if (ret
!= EXYNOS_DP_SUCCESS
) {
311 printk(BIOS_ERR
, "DP requst_link_traninig_req failed\n");
318 static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable
)
323 ret
= exynos_dp_read_byte_from_dpcd(DPCD_LANE_COUNT_SET
,
325 if (ret
!= EXYNOS_DP_SUCCESS
) {
326 printk(BIOS_ERR
, "DP read_from_dpcd failed\n");
331 data
= DPCD_ENHANCED_FRAME_EN
| DPCD_LN_COUNT_SET(data
);
333 data
= DPCD_LN_COUNT_SET(data
);
335 ret
= exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET
,
337 if (ret
!= EXYNOS_DP_SUCCESS
) {
338 printk(BIOS_ERR
, "DP write_to_dpcd failed\n");
345 static unsigned int exynos_dp_set_enhanced_mode(unsigned char enhance_mode
)
349 ret
= exynos_dp_enable_rx_to_enhanced_mode(enhance_mode
);
350 if (ret
!= EXYNOS_DP_SUCCESS
) {
351 printk(BIOS_ERR
, "DP rx_enhance_mode failed\n");
355 exynos_dp_enable_enhanced_mode(enhance_mode
);
360 static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info
*edp_info
,
361 unsigned char *status
)
364 unsigned char buf
[2];
365 unsigned char lane_stat
[DP_LANE_CNT_4
] = {0,};
366 const unsigned char shift_val
[] = {0, 4, 0, 4};
368 ret
= exynos_dp_read_bytes_from_dpcd(DPCD_LANE0_1_STATUS
, 2, buf
);
369 if (ret
!= EXYNOS_DP_SUCCESS
) {
370 printk(BIOS_ERR
, "DP read lane status failed\n");
374 for (i
= 0; i
< edp_info
->lane_cnt
; i
++) {
375 lane_stat
[i
] = (buf
[(i
/ 2)] >> shift_val
[i
]) & 0x0f;
376 if (lane_stat
[0] != lane_stat
[i
]) {
377 printk(BIOS_ERR
, "Wrong lane status\n");
382 *status
= lane_stat
[0];
387 static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num
,
388 unsigned char *sw
, unsigned char *em
)
390 const unsigned char shift_val
[] = {0, 4, 0, 4};
393 unsigned int dpcd_addr
;
395 /*lane_num value is used as array index, so this range 0 ~ 3 */
396 dpcd_addr
= DPCD_ADJUST_REQUEST_LANE0_1
+ (lane_num
/ 2);
398 ret
= exynos_dp_read_byte_from_dpcd(dpcd_addr
, &buf
);
399 if (ret
!= EXYNOS_DP_SUCCESS
) {
400 printk(BIOS_ERR
, "DP read adjust request failed\n");
404 *sw
= ((buf
>> shift_val
[lane_num
]) & 0x03);
405 *em
= ((buf
>> shift_val
[lane_num
]) & 0x0c) >> 2;
410 static int exynos_dp_equalizer_err_link(struct edp_device_info
*edp_info
)
414 ret
= exynos_dp_training_pattern_dis();
415 if (ret
!= EXYNOS_DP_SUCCESS
) {
416 printk(BIOS_ERR
, "DP training_patter_disable() failed\n");
417 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
420 ret
= exynos_dp_set_enhanced_mode(edp_info
->dpcd_efc
);
421 if (ret
!= EXYNOS_DP_SUCCESS
) {
422 printk(BIOS_ERR
, "DP set_enhanced_mode() failed\n");
423 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
429 static int exynos_dp_reduce_link_rate(struct edp_device_info
*edp_info
)
433 if (edp_info
->lane_bw
== DP_LANE_BW_2_70
) {
434 edp_info
->lane_bw
= DP_LANE_BW_1_62
;
435 printk(BIOS_ERR
, "DP Change lane bw to 1.62Gbps\n");
436 edp_info
->lt_info
.lt_status
= DP_LT_START
;
437 ret
= EXYNOS_DP_SUCCESS
;
439 ret
= exynos_dp_training_pattern_dis();
440 if (ret
!= EXYNOS_DP_SUCCESS
)
441 printk(BIOS_ERR
, "DP training_patter_disable() failed\n");
443 ret
= exynos_dp_set_enhanced_mode(edp_info
->dpcd_efc
);
444 if (ret
!= EXYNOS_DP_SUCCESS
)
445 printk(BIOS_ERR
, "DP set_enhanced_mode() failed\n");
447 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
453 static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
457 unsigned char lane_stat
;
458 unsigned char lt_ctl_val
[DP_LANE_CNT_4
] = {0, };
460 unsigned char adj_req_sw
;
461 unsigned char adj_req_em
;
462 unsigned char buf
[5];
466 ret
= exynos_dp_read_dpcd_lane_stat(edp_info
, &lane_stat
);
467 if (ret
!= EXYNOS_DP_SUCCESS
) {
468 printk(BIOS_ERR
, "DP read lane status failed\n");
469 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
473 if (lane_stat
& DP_LANE_STAT_CR_DONE
) {
474 printk(BIOS_DEBUG
,"DP clock Recovery training succeed\n");
475 exynos_dp_set_training_pattern(TRAINING_PTN2
);
477 for (i
= 0; i
< edp_info
->lane_cnt
; i
++) {
478 ret
= exynos_dp_read_dpcd_adj_req(i
, &adj_req_sw
,
480 if (ret
!= EXYNOS_DP_SUCCESS
) {
481 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
486 lt_ctl_val
[i
] = adj_req_em
<< 3 | adj_req_sw
;
488 if ((adj_req_sw
== VOLTAGE_LEVEL_3
)
489 || (adj_req_em
== PRE_EMPHASIS_LEVEL_3
)) {
490 lt_ctl_val
[i
] |= MAX_DRIVE_CURRENT_REACH_3
|
491 MAX_PRE_EMPHASIS_REACH_3
;
493 exynos_dp_set_lanex_pre_emphasis(lt_ctl_val
[i
], i
);
496 buf
[0] = DPCD_SCRAMBLING_DISABLED
| DPCD_TRAINING_PATTERN_2
;
497 buf
[1] = lt_ctl_val
[0];
498 buf
[2] = lt_ctl_val
[1];
499 buf
[3] = lt_ctl_val
[2];
500 buf
[4] = lt_ctl_val
[3];
502 ret
= exynos_dp_write_bytes_to_dpcd(
503 DPCD_TRAINING_PATTERN_SET
, 5, buf
);
504 if (ret
!= EXYNOS_DP_SUCCESS
) {
505 printk(BIOS_ERR
, "DP write training pattern1 failed\n");
506 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
509 edp_info
->lt_info
.lt_status
= DP_LT_ET
;
511 for (i
= 0; i
< edp_info
->lane_cnt
; i
++) {
512 lt_ctl_val
[i
] = exynos_dp_get_lanex_pre_emphasis(i
);
513 ret
= exynos_dp_read_dpcd_adj_req(i
,
514 &adj_req_sw
, &adj_req_em
);
515 if (ret
!= EXYNOS_DP_SUCCESS
) {
516 printk(BIOS_ERR
, "DP read adj req failed\n");
517 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
521 if ((adj_req_sw
== VOLTAGE_LEVEL_3
) ||
522 (adj_req_em
== PRE_EMPHASIS_LEVEL_3
))
523 ret
= exynos_dp_reduce_link_rate(edp_info
);
525 if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val
[i
]) ==
527 (PRE_EMPHASIS_SET_0_GET(lt_ctl_val
[i
]) ==
529 edp_info
->lt_info
.cr_loop
[i
]++;
530 if (edp_info
->lt_info
.cr_loop
[i
] == MAX_CR_LOOP
)
531 ret
= exynos_dp_reduce_link_rate(
536 lt_ctl_val
[i
] = adj_req_em
<< 3 | adj_req_sw
;
538 if ((adj_req_sw
== VOLTAGE_LEVEL_3
) ||
539 (adj_req_em
== PRE_EMPHASIS_LEVEL_3
)) {
540 lt_ctl_val
[i
] |= MAX_DRIVE_CURRENT_REACH_3
|
541 MAX_PRE_EMPHASIS_REACH_3
;
543 exynos_dp_set_lanex_pre_emphasis(lt_ctl_val
[i
], i
);
546 ret
= exynos_dp_write_bytes_to_dpcd(
547 DPCD_TRAINING_LANE0_SET
, 4, lt_ctl_val
);
548 if (ret
!= EXYNOS_DP_SUCCESS
) {
549 printk(BIOS_ERR
, "DP write training pattern2 failed\n");
550 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
558 static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
562 unsigned char lane_stat
, adj_req_sw
, adj_req_em
, i
;
563 unsigned char lt_ctl_val
[DP_LANE_CNT_4
] = {0,};
564 unsigned char interlane_aligned
= 0;
566 unsigned char f_lane_cnt
;
567 unsigned char sink_stat
;
571 ret
= exynos_dp_read_dpcd_lane_stat(edp_info
, &lane_stat
);
572 if (ret
!= EXYNOS_DP_SUCCESS
) {
573 printk(BIOS_ERR
, "DP read lane status failed\n");
574 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
578 printk(BIOS_DEBUG
,"DP lane stat : %x\n", lane_stat
);
580 if (lane_stat
& DP_LANE_STAT_CR_DONE
) {
581 printk(BIOS_DEBUG
, "DP_LANE_STAT_CR_DONE ok\n");
582 ret
= exynos_dp_read_byte_from_dpcd(DPCD_LN_ALIGN_UPDATED
,
584 if (ret
!= EXYNOS_DP_SUCCESS
) {
585 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
586 printk(BIOS_ERR
, "DP read DPCD_LN_ALIGN_UPDATED failed\n");
590 interlane_aligned
= (sink_stat
& DPCD_INTERLANE_ALIGN_DONE
);
591 printk(BIOS_DEBUG
, "interlane_aligned: %d\n", interlane_aligned
);
592 printk(BIOS_DEBUG
, "Check %d lanes\n", edp_info
->lane_cnt
);
594 for (i
= 0; i
< edp_info
->lane_cnt
; i
++) {
595 ret
= exynos_dp_read_dpcd_adj_req(i
,
596 &adj_req_sw
, &adj_req_em
);
597 if (ret
!= EXYNOS_DP_SUCCESS
) {
598 printk(BIOS_ERR
, "DP read adj req 1 failed\n");
599 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
605 lt_ctl_val
[i
] = adj_req_em
<< 3 | adj_req_sw
;
607 if ((adj_req_sw
== VOLTAGE_LEVEL_3
) ||
608 (adj_req_em
== PRE_EMPHASIS_LEVEL_3
)) {
609 lt_ctl_val
[i
] |= MAX_DRIVE_CURRENT_REACH_3
;
610 lt_ctl_val
[i
] |= MAX_PRE_EMPHASIS_REACH_3
;
614 if (((lane_stat
&DP_LANE_STAT_CE_DONE
) &&
615 (lane_stat
&DP_LANE_STAT_SYM_LOCK
))
616 && (interlane_aligned
== DPCD_INTERLANE_ALIGN_DONE
)) {
617 printk(BIOS_DEBUG
,"DP Equalizer training succeed\n");
619 f_bw
= exynos_dp_get_link_bandwidth();
620 f_lane_cnt
= exynos_dp_get_lane_count();
622 printk(BIOS_DEBUG
,"DP final BandWidth : %x\n", f_bw
);
623 printk(BIOS_DEBUG
,"DP final Lane Count : %x\n", f_lane_cnt
);
625 edp_info
->lt_info
.lt_status
= DP_LT_FINISHED
;
627 exynos_dp_equalizer_err_link(edp_info
);
630 edp_info
->lt_info
.ep_loop
++;
632 if (edp_info
->lt_info
.ep_loop
> MAX_EQ_LOOP
) {
633 if (edp_info
->lane_bw
== DP_LANE_BW_2_70
) {
634 ret
= exynos_dp_reduce_link_rate(
637 edp_info
->lt_info
.lt_status
=
639 exynos_dp_equalizer_err_link(edp_info
);
642 for (i
= 0; i
< edp_info
->lane_cnt
; i
++)
643 exynos_dp_set_lanex_pre_emphasis(
646 ret
= exynos_dp_write_bytes_to_dpcd(
647 DPCD_TRAINING_LANE0_SET
,
649 if (ret
!= EXYNOS_DP_SUCCESS
) {
650 printk(BIOS_ERR
, "DP set lt pattern failed\n");
651 edp_info
->lt_info
.lt_status
=
653 exynos_dp_equalizer_err_link(edp_info
);
657 } else if (edp_info
->lane_bw
== DP_LANE_BW_2_70
) {
658 ret
= exynos_dp_reduce_link_rate(edp_info
);
660 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
661 exynos_dp_equalizer_err_link(edp_info
);
667 static unsigned int exynos_dp_sw_link_training(struct edp_device_info
*edp_info
)
669 /* the C compiler is almost smart enough to know this gets set.
672 unsigned int ret
= 0;
673 int training_finished
;
675 /* Turn off unnecessary lane */
676 if (edp_info
->lane_cnt
== 1)
677 exynos_dp_set_analog_power_down(CH1_BLOCK
, 1);
679 training_finished
= 0;
681 edp_info
->lt_info
.lt_status
= DP_LT_START
;
684 while (!training_finished
) {
685 switch (edp_info
->lt_info
.lt_status
) {
687 ret
= exynos_dp_link_start(edp_info
);
688 if (ret
!= EXYNOS_DP_SUCCESS
) {
689 printk(BIOS_ERR
, "DP LT:link start failed\n");
690 training_finished
= 1;
694 ret
= exynos_dp_process_clock_recovery(edp_info
);
695 if (ret
!= EXYNOS_DP_SUCCESS
) {
696 printk(BIOS_ERR
, "DP LT:clock recovery failed\n");
697 training_finished
= 1;
701 ret
= exynos_dp_process_equalizer_training(edp_info
);
702 if (ret
!= EXYNOS_DP_SUCCESS
) {
703 printk(BIOS_ERR
, "DP LT:equalizer training failed\n");
704 training_finished
= 1;
708 training_finished
= 1;
711 printk(BIOS_ERR
,"DP: %s: DP_LT_FAIL: failed\n", __func__
);
712 training_finished
= 1;
720 static unsigned int exynos_dp_set_link_train(struct edp_device_info
*edp_info
)
724 exynos_dp_init_training();
726 ret
= exynos_dp_sw_link_training(edp_info
);
727 if (ret
!= EXYNOS_DP_SUCCESS
)
728 printk(BIOS_ERR
, "DP dp_sw_link_traning() failed\n");
733 static void exynos_dp_enable_scramble(unsigned int enable
)
738 exynos_dp_enable_scrambling(DP_ENABLE
);
740 exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET
,
742 exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET
,
743 (u8
)(data
& ~DPCD_SCRAMBLING_DISABLED
));
745 exynos_dp_enable_scrambling(DP_DISABLE
);
746 exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET
,
748 exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET
,
749 (u8
)(data
| DPCD_SCRAMBLING_DISABLED
));
753 static unsigned int exynos_dp_config_video(struct edp_device_info
*edp_info
)
755 unsigned int ret
= 0;
756 unsigned int retry_cnt
;
760 if (edp_info
->video_info
.master_mode
) {
762 "DP does not support master mode: bailing out\n");
766 exynos_dp_config_video_slave_mode(&edp_info
->video_info
);
769 exynos_dp_set_video_color_format(&edp_info
->video_info
);
771 ret
= exynos_dp_get_pll_lock_status();
772 if (ret
!= PLL_LOCKED
) {
773 printk(BIOS_ERR
, "DP PLL is not locked yet\n");
777 if (edp_info
->video_info
.master_mode
== 0) {
780 ret
= exynos_dp_is_slave_video_stream_clock_on();
781 if (ret
!= EXYNOS_DP_SUCCESS
) {
782 if (retry_cnt
== 0) {
783 printk(BIOS_ERR
, "DP stream_clock_on failed\n");
789 printk(BIOS_DEBUG
, "DP stream_clock succeeds\n");
795 /* Set to use the register calculated M/N video */
796 exynos_dp_set_video_cr_mn(CALCULATED_M
, 0, 0);
798 /* For video bist, Video timing must be generated by register
799 * not clear if we still need this. We could take it out and it
800 * might appear to work, then fail strangely.
802 exynos_dp_set_video_timing_mode(VIDEO_TIMING_FROM_CAPTURE
);
804 /* we need to be sure this is off. */
805 exynos_dp_disable_video_bist();
807 /* Disable video mute */
808 exynos_dp_enable_video_mute(DP_DISABLE
);
810 /* Configure video Master or Slave mode */
811 exynos_dp_enable_video_master(edp_info
->video_info
.master_mode
);
814 exynos_dp_start_video();
816 if (edp_info
->video_info
.master_mode
== 0) {
819 ret
= exynos_dp_is_video_stream_on();
820 if (ret
!= EXYNOS_DP_SUCCESS
) {
822 if (retry_cnt
== 0) {
823 printk(BIOS_ERR
, "DP Timeout of video stream\n");
826 printk(BIOS_DEBUG
, "DP video stream is on\n");
829 /* this is a cheap operation, involving some register
830 * reads, and no AUX channel IO. A ms. delay is fine.
839 int exynos_init_dp(struct edp_device_info
*edp_info
)
845 ret
= exynos_dp_init_dp();
846 if (ret
!= EXYNOS_DP_SUCCESS
) {
847 printk(BIOS_ERR
, "DP exynos_dp_init_dp() failed\n");
851 ret
= exynos_dp_handle_edid(edp_info
);
852 if (ret
!= EXYNOS_DP_SUCCESS
) {
853 printk(BIOS_ERR
, "EDP handle_edid fail\n");
857 ret
= exynos_dp_set_link_train(edp_info
);
858 if (ret
!= EXYNOS_DP_SUCCESS
) {
859 printk(BIOS_ERR
, "DP link training fail\n");
862 printk(BIOS_DEBUG
, "EDP link training ok\n");
864 exynos_dp_enable_scramble(DP_ENABLE
);
865 exynos_dp_enable_rx_to_enhanced_mode(DP_ENABLE
);
866 exynos_dp_enable_enhanced_mode(DP_ENABLE
);
868 exynos_dp_set_link_bandwidth(edp_info
->lane_bw
);
869 exynos_dp_set_lane_count(edp_info
->lane_cnt
);
871 exynos_dp_init_video();
872 ret
= exynos_dp_config_video(edp_info
);
874 if (ret
!= EXYNOS_DP_SUCCESS
) {
875 printk(BIOS_ERR
, "Exynos DP init failed\n");
878 printk(BIOS_DEBUG
, "Exynos DP init done\n");