src/southbridge/intel/i82371eb/ide.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /* TODO: Check if this really works for all of the southbridges. */
   4
   5 #include <stdint.h>
   6 #include <console/console.h>
   7 #include <device/device.h>
   8 #include <device/pci.h>
   9 #include <device/pci_ops.h>
  10 #include <device/pci_ids.h>
  11 #include "chip.h"
  12 #include "i82371eb.h"
  13
  14 /**
  15  * Initialize the IDE controller.
  16  *
  17  * Depending on the configuration variables 'ide0_enable' and 'ide1_enable'
  18  * enable or disable the primary and secondary IDE interface, respectively.
  19  *
  20  * Depending on the configuration variable 'ide_legacy_enable' enable or
  21  * disable access to the legacy IDE ports and the PCI Bus Master IDE I/O
  22  * registers (this is required for e.g. FILO).
  23  *
  24  * @param dev The device to use.
  25  */
  26 static void ide_init_enable(struct device *dev)
  27 {
  28         u16 reg16;
  29         struct southbridge_intel_i82371eb_config *conf = dev->chip_info;
  30
  31         /* Enable/disable the primary IDE interface. */
  32         reg16 = pci_read_config16(dev, IDETIM_PRI);
  33         reg16 = ONOFF(conf->ide0_enable, reg16, IDE_DECODE_ENABLE);
  34         pci_write_config16(dev, IDETIM_PRI, reg16);
  35         printk(BIOS_DEBUG, "IDE: %s: %s\n", "Primary interface",
  36                      conf->ide0_enable ? "on" : "off");
  37
  38         /* Enable/disable the secondary IDE interface. */
  39         reg16 = pci_read_config16(dev, IDETIM_SEC);
  40         reg16 = ONOFF(conf->ide1_enable, reg16, IDE_DECODE_ENABLE);
  41         pci_write_config16(dev, IDETIM_SEC, reg16);
  42         printk(BIOS_DEBUG, "IDE: %s: %s\n", "Secondary interface",
  43                      conf->ide1_enable ? "on" : "off");
  44
  45         /* Enable access to the legacy IDE ports (both primary and secondary),
  46          * and the PCI Bus Master IDE I/O registers.
  47          * Only do this if at least one IDE interface is enabled.
  48          */
  49         if (conf->ide0_enable || conf->ide1_enable) {
  50                 reg16 = pci_read_config16(dev, PCI_COMMAND);
  51                 reg16 = ONOFF(conf->ide_legacy_enable, reg16,
  52                               (PCI_COMMAND_IO | PCI_COMMAND_MASTER));
  53                 pci_write_config16(dev, PCI_COMMAND, reg16);
  54                 printk(BIOS_DEBUG, "IDE: Access to legacy IDE ports: %s\n",
  55                              conf->ide_legacy_enable ? "on" : "off");
  56         }
  57 }
  58
  59 /**
  60  * Initialize the Ultra DMA/33 support of the IDE controller.
  61  *
  62  * Depending on the configuration variables 'ide0_drive0_udma33_enable',
  63  * 'ide0_drive1_udma33_enable', 'ide1_drive0_udma33_enable', and
  64  * 'ide1_drive1_udma33_enable' enable or disable Ultra DMA/33 support for
  65  * the respective IDE controller and drive.
  66  *
  67  * Only do that if the respective controller is actually enabled, of course.
  68  *
  69  * @param dev The device to use.
  70  */
  71 static void ide_init_udma33(struct device *dev)
  72 {
  73         u8 reg8;
  74         struct southbridge_intel_i82371eb_config *conf = dev->chip_info;
  75
  76         /* Enable/disable UDMA/33 operation (primary IDE interface). */
  77         if (conf->ide0_enable) {
  78                 reg8 = pci_read_config8(dev, UDMACTL);
  79                 reg8 = ONOFF(conf->ide0_drive0_udma33_enable, reg8, PSDE0);
  80                 reg8 = ONOFF(conf->ide0_drive1_udma33_enable, reg8, PSDE1);
  81                 pci_write_config8(dev, UDMACTL, reg8);
  82
  83                 printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n",
  84                              "Primary interface", 0,
  85                              conf->ide0_drive0_udma33_enable ? "on" : "off");
  86                 printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n",
  87                              "Primary interface", 1,
  88                              conf->ide0_drive1_udma33_enable ? "on" : "off");
  89         }
  90
  91         /* Enable/disable Ultra DMA/33 operation (secondary IDE interface). */
  92         if (conf->ide1_enable) {
  93                 reg8 = pci_read_config8(dev, UDMACTL);
  94                 reg8 = ONOFF(conf->ide1_drive0_udma33_enable, reg8, SSDE0);
  95                 reg8 = ONOFF(conf->ide1_drive1_udma33_enable, reg8, SSDE1);
  96                 pci_write_config8(dev, UDMACTL, reg8);
  97
  98                 printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n",
  99                              "Secondary interface", 0,
 100                              conf->ide1_drive0_udma33_enable ? "on" : "off");
 101                 printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n",
 102                              "Secondary interface", 1,
 103                              conf->ide1_drive1_udma33_enable ? "on" : "off");
 104         }
 105 }
 106
 107 /**
 108  * IDE init for the Intel 82371FB/SB IDE controller.
 109  *
 110  * These devices do not support UDMA/33, so don't attempt to enable it.
 111  *
 112  * @param dev The device to use.
 113  */
 114 static void ide_init_i82371fb_sb(struct device *dev)
 115 {
 116         ide_init_enable(dev);
 117 }
 118
 119 /**
 120  * IDE init for the Intel 82371AB/EB/MB IDE controller.
 121  *
 122  * @param dev The device to use.
 123  */
 124 static void ide_init_i82371ab_eb_mb(struct device *dev)
 125 {
 126         ide_init_enable(dev);
 127         ide_init_udma33(dev);
 128 }
 129
 130 /* Intel 82371FB/SB */
 131 static const struct device_operations ide_ops_fb_sb = {
 132         .read_resources         = pci_dev_read_resources,
 133         .set_resources          = pci_dev_set_resources,
 134         .enable_resources       = pci_dev_enable_resources,
 135         .init                   = ide_init_i82371fb_sb,
 136         .ops_pci                = 0, /* No subsystem IDs on 82371XX! */
 137 };
 138
 139 /* Intel 82371AB/EB/MB */
 140 static const struct device_operations ide_ops_ab_eb_mb = {
 141         .read_resources         = pci_dev_read_resources,
 142         .set_resources          = pci_dev_set_resources,
 143         .enable_resources       = pci_dev_enable_resources,
 144         .init                   = ide_init_i82371ab_eb_mb,
 145         .ops_pci                = 0, /* No subsystem IDs on 82371XX! */
 146 };
 147
 148 /* Intel 82371FB (PIIX) */
 149 static const struct pci_driver ide_driver_fb __pci_driver = {
 150         .ops    = &ide_ops_fb_sb,
 151         .vendor = PCI_VID_INTEL,
 152         .device = PCI_DID_INTEL_82371FB_IDE,
 153 };
 154
 155 /* Intel 82371SB (PIIX3) */
 156 static const struct pci_driver ide_driver_sb __pci_driver = {
 157         .ops    = &ide_ops_fb_sb,
 158         .vendor = PCI_VID_INTEL,
 159         .device = PCI_DID_INTEL_82371SB_IDE,
 160 };
 161
 162 /* Intel 82371MX (MPIIX) */
 163 static const struct pci_driver ide_driver_mx __pci_driver = {
 164         .ops    = &ide_ops_fb_sb,
 165         .vendor = PCI_VID_INTEL,
 166         .device = PCI_DID_INTEL_82371MX_ISA_IDE,
 167 };
 168
 169 /* Intel 82437MX (part of the 430MX chipset) */
 170 static const struct pci_driver ide_driver_82437mx __pci_driver = {
 171         .ops    = &ide_ops_fb_sb,
 172         .vendor = PCI_VID_INTEL,
 173         .device = PCI_DID_INTEL_82437MX_ISA_IDE,
 174 };
 175
 176 /* Intel 82371AB/EB/MB */
 177 static const struct pci_driver ide_driver_ab_eb_mb __pci_driver = {
 178         .ops    = &ide_ops_ab_eb_mb,
 179         .vendor = PCI_VID_INTEL,
 180         .device = PCI_DID_INTEL_82371AB_IDE,
 181 };