src/southbridge/intel/i82801gx/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/pci_ops.h>
   5 #include <device/smbus_host.h>
   6 #include <southbridge/intel/common/gpio.h>
   7 #include <southbridge/intel/common/pmbase.h>
   8 #include <southbridge/intel/common/rcba.h>
   9
  10 #include "chip.h"
  11 #include "i82801gx.h"
  12
  13 void i82801gx_lpc_setup(void)
  14 {
  15         const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
  16         const struct device *dev = pcidev_on_root(0x1f, 0);
  17         const struct southbridge_intel_i82801gx_config *config;
  18
  19         /* Configure serial IRQs.*/
  20         pci_write_config8(d31f0, SERIRQ_CNTL, 0xd0);
  21         /*
  22          * Enable some common LPC IO ranges:
  23          * - 0x2e/0x2f, 0x4e/0x4f often SuperIO
  24          * - 0x60/0x64, 0x62/0x66 often KBC/EC
  25          * - 0x3f0-0x3f5/0x3f7 FDD
  26          * - 0x378-0x37f and 0x778-0x77f LPT
  27          * - 0x2f8-0x2ff COMB
  28          * - 0x3f8-0x3ff COMA
  29          * - 0x208-0x20f GAMEH
  30          * - 0x200-0x207 GAMEL
  31          */
  32         pci_write_config16(d31f0, LPC_IO_DEC, 0x0010);
  33         pci_write_config16(d31f0, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
  34                            | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN
  35                            | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
  36                            | COMB_LPC_EN | COMA_LPC_EN);
  37
  38         /* Set up generic decode ranges */
  39         if (!dev || !dev->chip_info)
  40                 return;
  41         config = dev->chip_info;
  42
  43         pci_write_config32(d31f0, GEN1_DEC, config->gen1_dec);
  44         pci_write_config32(d31f0, GEN2_DEC, config->gen2_dec);
  45         pci_write_config32(d31f0, GEN3_DEC, config->gen3_dec);
  46         pci_write_config32(d31f0, GEN4_DEC, config->gen4_dec);
  47 }
  48
  49 void i82801gx_setup_bars(void)
  50 {
  51         const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
  52         pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
  53         pci_write_config32(d31f0, PMBASE, DEFAULT_PMBASE | 1);
  54         pci_write_config8(d31f0, ACPI_CNTL, ACPI_EN);
  55
  56         pci_write_config32(d31f0, GPIOBASE, DEFAULT_GPIOBASE | 1);
  57         pci_write_config8(d31f0, GPIO_CNTL, GPIO_EN);
  58 }
  59
  60 #define TCO_BASE 0x60
  61
  62 #if ENV_RAMINIT
  63 void i82801gx_early_init(void)
  64 {
  65         enable_smbus();
  66
  67         printk(BIOS_DEBUG, "Setting up static southbridge registers...");
  68         i82801gx_setup_bars();
  69
  70         setup_pch_gpios(&mainboard_gpio_map);
  71         printk(BIOS_DEBUG, " done.\n");
  72
  73         printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
  74         RCBA32(GCS) = RCBA32(GCS) | (1 << 5);   /* No reset */
  75         write_pmbase16(TCO_BASE + 0x8, (1 << 11));      /* halt timer */
  76         write_pmbase16(TCO_BASE + 0x4, (1 << 3));       /* clear timeout */
  77         write_pmbase16(TCO_BASE + 0x6, (1 << 1));       /* clear 2nd timeout */
  78         printk(BIOS_DEBUG, " done.\n");
  79
  80         /* program secondary mlt XXX byte? */
  81         pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20);
  82
  83         /* reset rtc power status */
  84         pci_and_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, ~RTC_BATTERY_DEAD);
  85
  86         /* USB transient disconnect */
  87         pci_or_config8(PCI_DEV(0, 0x1f, 0), 0xad, 3 << 0);
  88
  89         pci_or_config32(PCI_DEV(0, 0x1d, 7), 0xfc, (1 << 29) | (1 << 17));
  90
  91         pci_or_config32(PCI_DEV(0, 0x1d, 7), 0xdc, (1 << 31) | (1 << 27));
  92
  93         /* Enable IOAPIC */
  94         RCBA8(OIC) = 0x03;
  95         RCBA8(OIC);
  96
  97         /* A lot of CIR bits relate DMI setup which is likely not correctly
  98            done for x4x. The issue is also present on ICH10. */
  99         if (!CONFIG(NORTHBRIDGE_INTEL_X4X))
 100                 ich7_setup_cir();
 101 }
 102 #endif