src/southbridge/intel/ibexpeak/pch.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/pci_ops.h>
   5 #include <device/device.h>
   6 #include <device/pci.h>
   7 #include "pch.h"
   8
   9 /* Set bit in function disable register to hide this device */
  10 static void pch_disable_devfn(struct device *dev)
  11 {
  12         switch (dev->path.pci.devfn) {
  13         case PCI_DEVFN(22, 0): /* MEI #1 */
  14                 RCBA32_OR(FD2, PCH_DISABLE_MEI1);
  15                 break;
  16         case PCI_DEVFN(22, 1): /* MEI #2 */
  17                 RCBA32_OR(FD2, PCH_DISABLE_MEI2);
  18                 break;
  19         case PCI_DEVFN(22, 2): /* IDE-R */
  20                 RCBA32_OR(FD2, PCH_DISABLE_IDER);
  21                 break;
  22         case PCI_DEVFN(22, 3): /* KT */
  23                 RCBA32_OR(FD2, PCH_DISABLE_KT);
  24                 break;
  25         case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
  26                 RCBA32_OR(BUC, PCH_DISABLE_GBE);
  27                 break;
  28         case PCI_DEVFN(26, 0): /* EHCI #2 */
  29                 RCBA32_OR(FD, PCH_DISABLE_EHCI2);
  30                 break;
  31         case PCI_DEVFN(27, 0): /* HD Audio Controller */
  32                 RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO);
  33                 break;
  34         case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
  35         case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
  36         case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
  37         case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
  38         case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
  39         case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
  40         case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */
  41         case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */
  42                 RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn)));
  43                 break;
  44         case PCI_DEVFN(29, 0): /* EHCI #1 */
  45                 RCBA32_OR(FD, PCH_DISABLE_EHCI1);
  46                 break;
  47         case PCI_DEVFN(31, 0): /* LPC */
  48                 RCBA32_OR(FD, PCH_DISABLE_LPC);
  49                 break;
  50         case PCI_DEVFN(31, 2): /* SATA #1 */
  51                 RCBA32_OR(FD, PCH_DISABLE_SATA1);
  52                 break;
  53         case PCI_DEVFN(31, 3): /* SMBUS */
  54                 RCBA32_OR(FD, PCH_DISABLE_SMBUS);
  55                 break;
  56         case PCI_DEVFN(31, 5): /* SATA #22 */
  57                 RCBA32_OR(FD, PCH_DISABLE_SATA2);
  58                 break;
  59         case PCI_DEVFN(31, 6): /* Thermal Subsystem */
  60                 RCBA32_OR(FD, PCH_DISABLE_THERMAL);
  61                 break;
  62         }
  63 }
  64
  65 void pch_enable(struct device *dev)
  66 {
  67         u16 reg16;
  68
  69         if (!dev->enabled) {
  70                 printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
  71
  72                 /* Ensure memory, io, and bus master are all disabled */
  73                 reg16 = pci_read_config16(dev, PCI_COMMAND);
  74                 reg16 &= ~(PCI_COMMAND_MASTER |
  75                            PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
  76                 pci_write_config16(dev, PCI_COMMAND, reg16);
  77
  78                 /* Disable this device if possible */
  79                 pch_disable_devfn(dev);
  80         } else {
  81                 /* Enable SERR */
  82                 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
  83         }
  84 }
  85
  86 struct chip_operations southbridge_intel_ibexpeak_ops = {
  87         .name = "Intel Series 5 (Ibexpeak) Southbridge",
  88         .enable_dev = pch_enable,
  89 };