src/superio/nuvoton/nct5104d/nct5104d.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #ifndef SUPERIO_NUVOTON_NCT5104D_H
   4 #define SUPERIO_NUVOTON_NCT5104D_H
   5
   6 #include <device/pnp_type.h>
   7
   8 /* SIO global configuration */
   9 #define IRQ_TYPE_SEL_CR10   0x10     /* UARTA,UARTB */
  10 #define IRQ_TYPE_SEL_CR11   0x11     /* SMI,UARTC,UARTD,WDTO */
  11 #define GLOBAL_OPTION_CR26  0x26
  12 #define CR26_LOCK_REG       (1 << 4) /* required to access CR10/CR11 */
  13
  14 /* LDN 0x07 specific registers */
  15 #define NCT5104D_GPIO0_IO   0xE0
  16 #define NCT5104D_GPIO1_IO   0xE4
  17 #define NCT5104D_GPIO6_IO   0xF8
  18
  19 /* LDN 0x0F specific registers */
  20 #define NCT5104D_GPIO0_PP_OD   0xE0
  21 #define NCT5104D_GPIO1_PP_OD   0xE1
  22 #define NCT5104D_GPIO6_PP_OD   0xE6
  23
  24 /* Logical Device Numbers (LDN). */
  25 #define NCT5104D_FDC        0x00 /* FDC - not pinned out */
  26 #define NCT5104D_SP1        0x02 /* UARTA */
  27 #define NCT5104D_SP2        0x03 /* UARTB */
  28 #define NCT5104D_GPIO_PP_OD 0x0F /* GPIO Push-Pull / Open drain select */
  29 #define NCT5104D_SP3        0x10 /* UARTC */
  30 #define NCT5104D_SP4        0x11 /* UARTD */
  31 #define NCT5104D_PORT80     0x14 /* PORT 80 */
  32
  33 /* Virtual Logical Device Numbers (LDN) */
  34 #define NCT5104D_GPIO_V 0x07 /* GPIO - 0,1,6 Interface */
  35 #define NCT5104D_GPIO_WDT_V 0x08 /* GPIO/WDT Interface */
  36
  37 /* Virtual devices sharing the enables are encoded as follows:
  38         VLDN = baseLDN[7:0] | [10:8] bitpos of enable in 0x30 of baseLDN
  39 */
  40 #define NCT5104D_GPIO0 ((0 << 8) | NCT5104D_GPIO_V)
  41 #define NCT5104D_GPIO1 ((1 << 8) | NCT5104D_GPIO_V)
  42 #define NCT5104D_GPIO6 ((6 << 8) | NCT5104D_GPIO_V)
  43
  44 #define NCT5104D_GPIO_WDT ((0 << 8) | NCT5104D_GPIO_WDT_V)
  45 #define NCT5104D_GPIO_IO  ((1 << 8) | NCT5104D_GPIO_WDT_V)
  46
  47 void nct5104d_enable_uartd(pnp_devfn_t dev);
  48
  49 #endif /* SUPERIO_NUVOTON_NCT5104D_H */