src/superio/nuvoton/nct6791d/superio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <device/device.h>
   4 #include <device/pnp.h>
   5 #include <pc80/keyboard.h>
   6 #include <superio/conf_mode.h>
   7 #include <superio/common/ssdt.h>
   8 #include <acpi/acpi.h>
   9 #include "nct6791d.h"
  10
  11 static void nct6791d_init(struct device *dev)
  12 {
  13         if (!dev->enabled)
  14                 return;
  15
  16         switch (dev->path.pnp.device) {
  17         case NCT6791D_KBC:
  18                 pc_keyboard_init(NO_AUX_DEVICE);
  19                 break;
  20         }
  21 }
  22
  23 #if CONFIG(HAVE_ACPI_TABLES)
  24 /* Provide ACPI HIDs for generic Super I/O SSDT */
  25 static const char *nct6791d_acpi_hid(const struct device *dev)
  26 {
  27         if ((dev->path.type != DEVICE_PATH_PNP) ||
  28                 (dev->path.pnp.port == 0) ||
  29                 ((dev->path.pnp.device & 0xff) > NCT6791D_DS))
  30                 return NULL;
  31
  32         switch (dev->path.pnp.device & 0xff) {
  33         case NCT6791D_SP1: /* fallthrough */
  34         case NCT6791D_SP2:
  35                 return ACPI_HID_COM;
  36         case NCT6791D_KBC:
  37                 return ACPI_HID_KEYBOARD;
  38         default:
  39                 return ACPI_HID_PNP;
  40         }
  41 }
  42 #endif
  43
  44 static struct device_operations ops = {
  45         .read_resources   = pnp_read_resources,
  46         .set_resources    = pnp_set_resources,
  47         .enable_resources = pnp_enable_resources,
  48         .enable           = pnp_alt_enable,
  49         .init             = nct6791d_init,
  50         .ops_pnp_mode     = &pnp_conf_mode_8787_aa,
  51 #if CONFIG(HAVE_ACPI_TABLES)
  52         .acpi_fill_ssdt   = superio_common_fill_ssdt_generator,
  53         .acpi_name        = superio_common_ldn_acpi_name,
  54         .acpi_hid         = nct6791d_acpi_hid,
  55 #endif
  56 };
  57
  58 static struct pnp_info pnp_dev_info[] = {
  59         { NULL, NCT6791D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0,
  60                 0x0ff8, },
  61         { NULL, NCT6791D_SP1, PNP_IO0 | PNP_IRQ0,
  62                 0x0ff8, },
  63         { NULL, NCT6791D_SP2, PNP_IO0 | PNP_IRQ0,
  64                 0x0ff8, },
  65         { NULL, NCT6791D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
  66                 0x0fff, 0x0fff, },
  67         { NULL, NCT6791D_CIR, PNP_IO0 | PNP_IRQ0,
  68                 0x0ff8, },
  69         { NULL, NCT6791D_ACPI},
  70         { NULL, NCT6791D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
  71                 0x0ffe, 0x0ffe, },
  72         { NULL, NCT6791D_BCLK_WDT2_WDTMEM},
  73         { NULL, NCT6791D_CIRWUP, PNP_IO0 | PNP_IRQ0,
  74                 0x0ff8, },
  75         { NULL, NCT6791D_GPIO_PP_OD},
  76         { NULL, NCT6791D_PORT80},
  77         { NULL, NCT6791D_WDT1},
  78         { NULL, NCT6791D_WDTMEM},
  79         { NULL, NCT6791D_GPIOBASE, PNP_IO0,
  80                 0x0ff8, },
  81         { NULL, NCT6791D_GPIO0},
  82         { NULL, NCT6791D_GPIO1},
  83         { NULL, NCT6791D_GPIO2},
  84         { NULL, NCT6791D_GPIO3},
  85         { NULL, NCT6791D_GPIO4},
  86         { NULL, NCT6791D_GPIO5},
  87         { NULL, NCT6791D_GPIO6},
  88         { NULL, NCT6791D_GPIO7},
  89         { NULL, NCT6791D_GPIO8},
  90         { NULL, NCT6791D_DS5},
  91         { NULL, NCT6791D_DS3},
  92         { NULL, NCT6791D_PCHDSW},
  93         { NULL, NCT6791D_DSWWOPT},
  94         { NULL, NCT6791D_DS3OPT},
  95         { NULL, NCT6791D_DSDSS},
  96         { NULL, NCT6791D_DSPU},
  97 };
  98
  99 static void enable_dev(struct device *dev)
 100 {
 101         pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 102 }
 103
 104 struct chip_operations superio_nuvoton_nct6791d_ops = {
 105         .name = "NUVOTON NCT6791D Super I/O",
 106         .enable_dev = enable_dev,
 107 };