src/vendorcode/mediatek/mt8195/include/dramc_actiming.h

   1 /* SPDX-License-Identifier: BSD-3-Clause */
   2
   3 #ifndef _ACTIMING_H
   4 #define _ACTIMING_H
   5
   6 /***********************************************************************/
   7 /*              Includes                                               */
   8 /***********************************************************************/
   9 #include "dramc_register.h"
  10
  11
  12 //Definitions to enable specific freq's LP4 ACTiming support (To save code size)
  13 #define SUPPORT_LP5_DDR6400_ACTIM 0
  14 #define SUPPORT_LP5_DDR5500_ACTIM 0
  15 #define SUPPORT_LP5_DDR4266_ACTIM 0
  16 #define SUPPORT_LP5_DDR3200_ACTIM 0
  17 #define SUPPORT_LP4_DDR4266_ACTIM 1
  18 #define SUPPORT_LP4_DDR3733_ACTIM 1
  19 #define SUPPORT_LP4_DDR3200_ACTIM 1
  20 #define SUPPORT_LP4_DDR2667_ACTIM 0
  21 #define SUPPORT_LP4_DDR2400_ACTIM 1
  22 #define SUPPORT_LP4_DDR1866_ACTIM 1
  23 #define SUPPORT_LP4_DDR1600_ACTIM 1
  24 #define SUPPORT_LP4_DDR1333_ACTIM 0
  25 #define SUPPORT_LP4_DDR1200_ACTIM 1
  26 #define SUPPORT_LP4_DDR800_ACTIM  1
  27 #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION
  28 #define SUPPORT_LP4_DDR400_ACTIM  1
  29 #else
  30 #define SUPPORT_LP4_DDR400_ACTIM  0
  31 #endif
  32 /* Used to keep track the total number of LP4 ACTimings */
  33 /* Since READ_DBI is enable/disabled using preprocessor C define
  34  * -> Save code size by excluding unneeded ACTimingTable entries
  35  * Note 1: READ_DBI on/off is for (LP4 data rate >= DDR2667 (FSP1))
  36  * Must make sure DDR3733 is the 1st entry (DMCATRAIN_INTV is used)
  37  */
  38 typedef enum
  39 {
  40 #if SUPPORT_LP4_DDR4266_ACTIM
  41 #if ENABLE_READ_DBI
  42     AC_TIME_LP4_BYTE_DDR4266_RDBI_ON = 0,
  43     AC_TIME_LP4_NORM_DDR4266_RDBI_ON,
  44 #else //(ENABLE_READ_DBI == 0)
  45     AC_TIME_LP4_BYTE_DDR4266_RDBI_OFF,
  46     AC_TIME_LP4_NORM_DDR4266_RDBI_OFF,
  47 #endif //ENABLE_READ_DBI
  48 #endif
  49
  50 #if SUPPORT_LP4_DDR3733_ACTIM
  51 #if ENABLE_READ_DBI
  52     AC_TIME_LP4_BYTE_DDR3733_RDBI_ON,
  53     AC_TIME_LP4_NORM_DDR3733_RDBI_ON,
  54 #else //(ENABLE_READ_DBI == 0)
  55     AC_TIME_LP4_BYTE_DDR3733_RDBI_OFF,
  56     AC_TIME_LP4_NORM_DDR3733_RDBI_OFF,
  57 #endif //ENABLE_READ_DBI
  58 #endif
  59
  60 #if SUPPORT_LP4_DDR3200_ACTIM
  61 #if ENABLE_READ_DBI
  62     AC_TIME_LP4_BYTE_DDR3200_RDBI_ON,
  63     AC_TIME_LP4_NORM_DDR3200_RDBI_ON,
  64 #else //(ENABLE_READ_DBI == 0)
  65     AC_TIME_LP4_BYTE_DDR3200_RDBI_OFF,
  66     AC_TIME_LP4_NORM_DDR3200_RDBI_OFF,
  67 #endif //ENABLE_READ_DBI
  68 #endif
  69
  70 #if SUPPORT_LP4_DDR2667_ACTIM
  71 #if ENABLE_READ_DBI
  72     AC_TIME_LP4_BYTE_DDR2667_RDBI_ON,
  73     AC_TIME_LP4_NORM_DDR2667_RDBI_ON,
  74 #else //(ENABLE_READ_DBI == 0)
  75     AC_TIME_LP4_BYTE_DDR2667_RDBI_OFF,
  76     AC_TIME_LP4_NORM_DDR2667_RDBI_OFF,
  77 #endif //ENABLE_READ_DBI
  78 #endif
  79
  80 #if SUPPORT_LP4_DDR2400_ACTIM
  81     AC_TIME_LP4_BYTE_DDR2400_RDBI_OFF,
  82     AC_TIME_LP4_NORM_DDR2400_RDBI_OFF,
  83 #endif
  84
  85 #if SUPPORT_LP4_DDR1866_ACTIM
  86     AC_TIME_LP4_BYTE_DDR1866_RDBI_OFF,
  87     AC_TIME_LP4_NORM_DDR1866_RDBI_OFF,
  88 #endif
  89
  90 #if SUPPORT_LP4_DDR1600_ACTIM
  91     AC_TIME_LP4_BYTE_DDR1600_RDBI_OFF,
  92     AC_TIME_LP4_NORM_DDR1600_RDBI_OFF,
  93     AC_TIME_LP4_BYTE_DDR1600_DIV4_RDBI_OFF,
  94     AC_TIME_LP4_NORM_DDR1600_DIV4_RDBI_OFF,
  95 #endif
  96
  97 #if SUPPORT_LP4_DDR1333_ACTIM
  98     AC_TIME_LP4_BYTE_DDR1333_RDBI_OFF,
  99     AC_TIME_LP4_NORM_DDR1333_RDBI_OFF,
 100 #endif
 101
 102
 103 #if SUPPORT_LP4_DDR1200_ACTIM
 104     AC_TIME_LP4_BYTE_DDR1200_RDBI_OFF,
 105     AC_TIME_LP4_NORM_DDR1200_RDBI_OFF,
 106     AC_TIME_LP4_BYTE_DDR1200_DIV4_RDBI_OFF,
 107     AC_TIME_LP4_NORM_DDR1200_DIV4_RDBI_OFF,
 108 #endif
 109
 110 #if SUPPORT_LP4_DDR800_ACTIM
 111     AC_TIME_LP4_BYTE_DDR800_RDBI_OFF,
 112     AC_TIME_LP4_NORM_DDR800_RDBI_OFF,
 113     AC_TIME_LP4_BYTE_DDR800_DIV4_RDBI_OFF,
 114     AC_TIME_LP4_NORM_DDR800_DIV4_RDBI_OFF,
 115 #endif
 116
 117 #if SUPPORT_LP4_DDR400_ACTIM
 118     AC_TIME_LP4_BYTE_DDR400_RDBI_OFF,
 119     AC_TIME_LP4_NORM_DDR400_RDBI_OFF,
 120 #endif
 121
 122     AC_TIMING_NUMBER_LP4
 123 } AC_TIMING_LP4_COUNT_TYPE_T;
 124
 125 #define AC_TIMING_NUMBER_LP5    0
 126
 127 /* ACTiming struct declaration (declared here due Fld_wid for each register type)
 128  * Should include all fields from ACTiming excel file (And update the correct values in UpdateACTimingReg()
 129  * Note: DQSINCTL, DATLAT aren't in ACTiming excel file (internal delay parameters)
 130  */
 131 typedef struct _ACTime_T_LP4
 132 {
 133     U8 dramType, cbtMode, readDBI;
 134     U8 DivMode;
 135     U16 freq;
 136     U8 readLat, writeLat;
 137     U8 dqsinctl, datlat; //DQSINCTL, DATLAT aren't in ACTiming excel file
 138
 139     U8 tras;
 140     U8 trp;
 141     U8 trpab;
 142     U8 trc;
 143     U8 trfc;
 144     U8 trfcpb;
 145     U8 txp;
 146     U8 trtp;
 147     U8 trcd;
 148     U8 twr;
 149     U8 twtr;
 150     U8 tpbr2pbr;
 151     U8 tpbr2act;
 152     U8 tr2mrw;
 153     U8 tw2mrw;
 154     U8 tmrr2mrw;
 155     U8 tmrw;
 156     U8 tmrd;
 157     U8 tmrwckel;
 158     U8 tpde;
 159     U8 tpdx;
 160     U8 tmrri;
 161     U8 trrd;
 162     U8 trrd_4266;
 163     U8 tfaw;
 164     U8 tfaw_4266;
 165     U8 trtw_odt_off;
 166     U8 trtw_odt_on;
 167     U16 txrefcnt;
 168     U8 tzqcs;
 169     U8 xrtw2w_new_mode;
 170     U8 xrtw2w_old_mode;
 171     U8 xrtw2r_odt_on;
 172     U8 xrtw2r_odt_off;
 173     U8 xrtr2w_odt_on;
 174     U8 xrtr2w_odt_off;
 175     U8 xrtr2r_new_mode;
 176     U8 xrtr2r_old_mode;
 177     U8 tr2mrr;
 178     U8 vrcgdis_prdcnt;
 179     U8 hwset_mr2_op;
 180     U8 hwset_mr13_op;
 181     U8 hwset_vrcg_op;
 182     U8 trcd_derate;
 183     U8 trc_derate;
 184     U8 tras_derate;
 185     U8 trpab_derate;
 186     U8 trp_derate;
 187     U8 trrd_derate;
 188     U8 trtpd;
 189     U8 twtpd;
 190     U8 tmrr2w_odt_off;
 191     U8 tmrr2w_odt_on;
 192     U8 ckeprd;
 193     U8 ckelckcnt;
 194     U8 zqlat2;
 195
 196     //DRAMC_REG_SHU_AC_TIME_05T ===================================
 197     U8 tras_05T;
 198     U8 trp_05T;
 199     U8 trpab_05T;
 200     U8 trc_05T;
 201     U8 trfc_05T;
 202     U8 trfcpb_05T;
 203     U8 txp_05T;
 204     U8 trtp_05T;
 205     U8 trcd_05T;
 206     U8 twr_05T;
 207     U8 twtr_05T;
 208     U8 tpbr2pbr_05T;
 209     U8 tpbr2act_05T;
 210     U8 tr2mrw_05T;
 211     U8 tw2mrw_05T;
 212     U8 tmrr2mrw_05T;
 213     U8 tmrw_05T;
 214     U8 tmrd_05T;
 215     U8 tmrwckel_05T;
 216     U8 tpde_05T;
 217     U8 tpdx_05T;
 218     U8 tmrri_05T;
 219     U8 trrd_05T;
 220     U8 trrd_4266_05T;
 221     U8 tfaw_05T;
 222     U8 tfaw_4266_05T;
 223     U8 trtw_odt_off_05T;
 224     U8 trtw_odt_on_05T;
 225     U8 trcd_derate_05T;
 226     U8 trc_derate_05T;
 227     U8 tras_derate_05T;
 228     U8 trpab_derate_05T;
 229     U8 trp_derate_05T;
 230     U8 trrd_derate_05T;
 231     U8 trtpd_05T;
 232     U8 twtpd_05T;
 233 } ACTime_T_LP4;
 234
 235 typedef struct _ACTime_T_LP5
 236 {
 237     U8 dramType, cbtMode, readDBI;
 238     U8 DivMode;
 239     U16 freq;
 240     U8 readLat, writeLat;
 241     U8 dqsinctl, datlat; //DQSINCTL, DATLAT aren't in ACTiming excel file
 242
 243     U8 tras;
 244     U8 trp;
 245     U8 trpab;
 246     U8 trc;
 247     U8 trfc;
 248     U8 trfcpb;
 249     U8 txp;
 250     U8 trtp;
 251     U8 trcd;
 252     U8 twr;
 253     U8 twtr;
 254     U8 twtr_l;
 255     U8 tpbr2pbr;
 256     U8 tpbr2act;
 257     U8 tr2mrw;
 258     U8 tw2mrw;
 259     U8 tmrr2mrw;
 260     U8 tmrw;
 261     U8 tmrd;
 262     U8 tmrwckel;
 263     U8 tpde;
 264     U8 tpdx;
 265     U8 tmrri;
 266     U8 trrd;
 267     U8 tfaw;
 268     U8 tr2w_odt_off;
 269     U8 tr2w_odt_on;
 270     U16 txrefcnt;
 271     U8 wckrdoff;
 272     U8 wckwroff;
 273     U8 tzqcs;
 274     U8 xrtw2w_odt_off;
 275     U8 xrtw2w_odt_on;
 276     U8 xrtw2r_odt_off_otf_off;
 277     U8 xrtw2r_odt_on_otf_off;
 278     U8 xrtw2r_odt_off_otf_on;
 279     U8 xrtw2r_odt_on_otf_on;
 280     U8 xrtr2w_odt_on;
 281     U8 xrtr2w_odt_off;
 282     U8 xrtr2r_odt_off;
 283     U8 xrtr2r_odt_on;
 284     U8 xrtw2w_odt_off_wck;
 285     U8 xrtw2w_odt_on_wck;
 286     U8 xrtw2r_odt_off_wck;
 287     U8 xrtw2r_odt_on_wck;
 288     U8 xrtr2w_odt_off_wck;
 289     U8 xrtr2w_odt_on_wck;
 290     U8 xrtr2r_wck;
 291     U8 tr2mrr;
 292     U8 hwset_mr2_op;
 293     U8 hwset_mr13_op;
 294     U8 hwset_vrcg_op;
 295     U8 vrcgdis_prdcnt;
 296     U8 lp5_cmd1to2en;
 297     U8 trtpd;
 298     U8 twtpd;
 299     U8 tmrr2w;
 300     U8 ckeprd;
 301     U8 ckelckcnt;
 302     U8 tcsh_cscal;
 303     U8 tcacsh;
 304     U8 tcsh;
 305     U8 trcd_derate;
 306     U8 trc_derate;
 307     U8 tras_derate;
 308     U8 trpab_derate;
 309     U8 trp_derate;
 310     U8 trrd_derate;
 311     U8 zqlat2;
 312
 313     //DRAMC_REG_SHU_AC_TIME_05T ===================================
 314     U8 tras_05T;
 315     U8 trp_05T;
 316     U8 trpab_05T;
 317     U8 trc_05T;
 318     U8 trfc_05T;
 319     U8 trfcpb_05T;
 320     U8 txp_05T;
 321     U8 trtp_05T;
 322     U8 trcd_05T;
 323     U8 twr_05T;
 324     U8 twtr_05T;
 325     U8 twtr_l_05T;
 326     U8 tr2mrw_05T;
 327     U8 tw2mrw_05T;
 328     U8 tmrr2mrw_05T;
 329     U8 tmrw_05T;
 330     U8 tmrd_05T;
 331     U8 tmrwckel_05T;
 332     U8 tpde_05T;
 333     U8 tpdx_05T;
 334     U8 tmrri_05T;
 335     U8 trrd_05T;
 336     U8 tfaw_05T;
 337     U8 tr2w_odt_off_05T;
 338     U8 tr2w_odt_on_05T;
 339     U8 wckrdoff_05T;
 340     U8 wckwroff_05T;
 341     U8 trtpd_05T;
 342     U8 twtpd_05T;
 343     U8 tpbr2pbr_05T;
 344     U8 tpbr2act_05T;
 345     U8 trcd_derate_05T;
 346     U8 trc_derate_05T;
 347     U8 tras_derate_05T;
 348     U8 trpab_derate_05T;
 349     U8 trp_derate_05T;
 350     U8 trrd_derate_05T;
 351 } ACTime_T_LP5;
 352
 353 //ACTimingTbl[] forward declaration
 354
 355 extern U8 vDramcACTimingGetDatLat(DRAMC_CTX_T *p);
 356 extern DRAM_STATUS_T DdrUpdateACTiming(DRAMC_CTX_T *p);
 357 #endif