src/vendorcode/mediatek/mt8195/include/dramc_top.h

   1 /* SPDX-License-Identifier: BSD-3-Clause */
   2
   3 #ifndef __DRAMC_TOP_H__
   4 #define __DRAMC_TOP_H__
   5 #ifdef FLASH_TOOL_DA
   6   #include "sw_types.h"
   7 #else
   8   #include "dramc_typedefs.h"
   9 #endif
  10 #include "dramc_common.h"
  11
  12
  13 #if __ETT__
  14 #if (FOR_DV_SIMULATION_USED==0)
  15 #define DRAM_ADAPTIVE
  16 #endif
  17 #endif
  18
  19 #define DRAM_ADAPTIVE
  20
  21 #define DRAM_BASE 0x40000000ULL
  22 #define DDR_BASE DRAM_BASE
  23
  24 #if __ETT__
  25 #define dramc_crit              printf
  26 #define dramc_debug             printf
  27 #elif __FLASH_TOOL_DA__
  28 #define dramc_crit              LOGD
  29 #define dramc_debug             LOGD
  30 #else
  31 #define dramc_crit              print
  32 #define dramc_debug             printf
  33 #endif
  34
  35
  36 #define DRAMC_MAX_CH    4
  37 #define DRAMC_MAX_RK    2
  38 #define DRAMC_MR_CNT    4
  39 #define DRAMC_FREQ_CNT  7
  40
  41 struct mr_info_t {
  42         u16 mr_index;
  43         u16 mr_value;
  44 };
  45 //[FOR_CHROMEOS]
  46 extern struct dramc_param *dramc_params;
  47
  48 enum DRAM_TYPE {
  49         DTYPE_DDR1 = 1,
  50         DTYPE_LPDDR2,
  51         DTYPE_LPDDR3,
  52         DTYPE_PCDDR3,
  53         DTYPE_LPDDR4,
  54         DTYPE_LPDDR4X,
  55         DTYPE_LPDDR4P
  56 };
  57
  58 int mt_get_dram_type(void);
  59 int get_dram_channel_support_nr(void);
  60 int get_dram_channel_nr(void);
  61 int get_dram_rank_nr(void);
  62 int get_dram_mr_cnt(void);
  63 int get_dram_freq_cnt(void);
  64 #if !__ETT__
  65 void get_dram_rank_size(u64 dram_rank_size[DRAMC_MAX_RK]);
  66 void get_dram_freq_step(u32 dram_freq_step[]);
  67 void set_dram_mr(unsigned int index, unsigned short value);
  68 unsigned short get_dram_mr(unsigned int index);
  69 void get_dram_mr_info(struct mr_info_t mr_info[]);
  70 void reserve_dramc_dummy_read(void);
  71 #endif
  72 typedef struct _AC_TIMING_EXTERNAL_T
  73 {
  74     // U 00
  75     U32 AC_TIME_EMI_FREQUENCY      :16;
  76     U32 AC_TIME_EMI_TRAS           :8;
  77     U32 AC_TIME_EMI_TRP            :8;
  78
  79     // U 01
  80     U32 AC_TIME_EMI_TRPAB          :8;
  81     U32 AC_TIME_EMI_TRC            :8;
  82     U32 AC_TIME_EMI_TRFC           :8;
  83     U32 AC_TIME_EMI_TRFCPB         :8;
  84
  85     // U 02
  86     U32 AC_TIME_EMI_TXP            :8;
  87     U32 AC_TIME_EMI_TRTP           :8;
  88     U32 AC_TIME_EMI_TRCD           :8;
  89     U32 AC_TIME_EMI_TWR            :8;
  90
  91     // U 03
  92     U32 AC_TIME_EMI_TWTR           :8;
  93     U32 AC_TIME_EMI_TRRD           :8;
  94     U32 AC_TIME_EMI_TFAW           :8;
  95     U32 AC_TIME_EMI_TRTW_ODT_OFF   :4;
  96     U32 AC_TIME_EMI_TRTW_ODT_ON    :4;
  97
  98     // U 04
  99     U32 AC_TIME_EMI_REFCNT         :8;
 100     U32 AC_TIME_EMI_REFCNT_FR_CLK  :8;
 101     U32 AC_TIME_EMI_TXREFCNT       :8;
 102     U32 AC_TIME_EMI_TZQCS          :8;
 103
 104     // U 05
 105     U32 AC_TIME_EMI_TRTPD            :8;
 106     U32 AC_TIME_EMI_TWTPD            :8;
 107     U32 AC_TIME_EMI_TMRR2W_ODT_OFF   :8;
 108     U32 AC_TIME_EMI_TMRR2W_ODT_ON    :8;
 109
 110     // U 06
 111     // Byte0
 112     U32 AC_TIME_EMI_TRAS_05T          :2;
 113     U32 AC_TIME_EMI_TRP_05T           :2;
 114     U32 AC_TIME_EMI_TRPAB_05T         :2;
 115     U32 AC_TIME_EMI_TRC_05T           :2;
 116     // Byte1
 117     U32 AC_TIME_EMI_TRFC_05T          :2;
 118     U32 AC_TIME_EMI_TRFCPB_05T        :2;
 119     U32 AC_TIME_EMI_TXP_05T           :2;
 120     U32 AC_TIME_EMI_TRTP_05T          :2;
 121     // Byte2
 122     U32 AC_TIME_EMI_TRCD_05T          :2;
 123     U32 AC_TIME_EMI_TWR_05T           :2;
 124     U32 AC_TIME_EMI_TWTR_05T          :2;
 125     U32 AC_TIME_EMI_TRRD_05T          :2;
 126     // Byte3
 127     U32 AC_TIME_EMI_TFAW_05T          :2;
 128     U32 AC_TIME_EMI_TRTW_ODT_OFF_05T  :2;
 129     U32 AC_TIME_EMI_TRTW_ODT_ON_05T   :2;
 130     U32 AC_TIME_EMI_TRTPD_05T         :2;
 131
 132     // U 07
 133     // Byte0
 134     U32 AC_TIME_EMI_TWTPD_05T           :2;
 135     U32 AC_TIME_EMI_TMRR2W_ODT_OFF_05T  :2;
 136     U32 AC_TIME_EMI_TMRR2W_ODT_ON_05T   :2;
 137
 138
 139 }AC_TIMING_EXTERNAL_T;
 140
 141 //[FOR_CHROMEOS] Move EMI_SETTINGS to dramc_custom.h
 142 typedef struct {
 143     unsigned int type; /* 0x0000 : Invalid
 144                           0x0001 : Discrete DDR1
 145                           0x0002 : Discrete LPDDR2
 146                           0x0003 : Discrete LPDDR3
 147                           0x0004 : Discrete PCDDR3
 148                           0x0005 : Discrete LPDDR4
 149                           0x0006 : Discrete LPDR4X
 150                           0x0101 : MCP(NAND+DDR1)
 151                           0x0102 : MCP(NAND+LPDDR2)
 152                           0x0103 : MCP(NAND+LPDDR3)
 153                           0x0104 : MCP(NAND+PCDDR3)
 154                           0x0201 : MCP(eMMC+DDR1)
 155                           0x0202 : MCP(eMMC+LPDDR2)
 156                           0x0203 : MCP(eMMC+LPDDR3)
 157                           0x0204 : MCP(eMMC+PCDDR3)
 158                           0x0205 : MCP(eMMC+LPDDR4)
 159                           0x0206 : MCP(eMMC+LPDR4X) */
 160     unsigned int EMI_CONA_VAL;
 161     unsigned int EMI_CONH_VAL;
 162     unsigned int EMI_CONK_VAL;
 163     unsigned int EMI_CONF_VAL;
 164     unsigned int CHN0_EMI_CONA_VAL;
 165     unsigned int CHN1_EMI_CONA_VAL;
 166     u64 DRAM_RANK_SIZE[4];
 167     unsigned int dram_cbt_mode_extern;
 168     unsigned int iLPDDR3_MODE_REG_5;
 169     unsigned int highest_freq;
 170 } EMI_SETTINGS;
 171
 172 typedef struct {
 173     unsigned int type;
 174     unsigned int id_length;
 175     unsigned char ID[16];
 176     u64 DRAM_RANK_SIZE[4];
 177     unsigned int reserved[6];
 178     unsigned int iLPDDR3_MODE_REG_5;
 179 } QVL_LIST_T;
 180
 181 //typedef  EMI_SETTINGS_v15 EMI_SETTINGS;
 182 #if (FOR_DV_SIMULATION_USED==0)
 183 void setup_dramc_voltage_by_pmic(void);
 184 void switch_dramc_voltage_to_auto_mode(void);
 185 #if ! __ETT__
 186 uint32 mt_set_emis(uint8* emi, uint32 len, bool use_default);
 187 #endif
 188 #endif
 189
 190 extern int num_of_emi_records;
 191 extern EMI_SETTINGS g_default_emi_setting;
 192 extern unsigned int channel_num_auxadc;
 193 #if DRAM_AUXADC_CONFIG
 194 extern unsigned int dram_type_auxadc;
 195 #endif
 196
 197 #include "x_hal_io.h"
 198
 199 void init_ta2_single_channel(unsigned int);
 200 #ifdef LAST_DRAMC
 201 #define LAST_DRAMC_MAGIC_PATTERN 0x19870611
 202 static void update_last_dramc_info(void);
 203 void init_ta2_all_channel(void);
 204 typedef struct {
 205     unsigned long long ta2_result_magic;
 206     unsigned long long ta2_result_last;
 207     unsigned long long ta2_result_past;
 208     unsigned long long ta2_result_checksum;
 209     unsigned long long reboot_count;
 210     volatile unsigned int last_fatal_err_flag;
 211     volatile unsigned int fatal_err_flag;
 212     volatile unsigned int storage_api_err_flag;
 213     volatile unsigned int last_gating_err[4][2];
 214     volatile unsigned int gating_err[4][2];
 215     unsigned short mr5;
 216     unsigned short mr6;
 217     unsigned short mr7;
 218     unsigned short mr8;
 219 } LAST_DRAMC_INFO_T;
 220 #define DEF_LAST_DRAMC LAST_DRAMC_INFO_T
 221
 222 #define OFFSET_DRAM_FATAL_ERR           (31)
 223 #define OFFSET_DRAM_TA2_ERR             (23)
 224 #define OFFSET_DRAM_GATING_ERR          (7)
 225 #define OFFSET_CPU_RW_ERR               (5)
 226 #define OFFSET_DDR_RSV_MODE_FLOW        (4)
 227 #define OFFSET_DDR_RSV_MODE_ERR         (3)
 228 #define OFFSET_EMI_DCS_ERR              (2)
 229 #define OFFSET_DVFSRC_ERR               (1)
 230 #define OFFSET_DRS_ERR                  (0)
 231
 232 #define ERR_DRAM_TA2_RK0                (1 << 0)
 233 #define ERR_DRAM_TA2_RK1                (1 << 1)
 234
 235 #define ERR_DRAM_GATING_RK0_R           (1 << 0)
 236 #define ERR_DRAM_GATING_RK0_F           (1 << 1)
 237 #define ERR_DRAM_GATING_RK1_R           (1 << 2)
 238 #define ERR_DRAM_GATING_RK1_F           (1 << 3)
 239
 240 #define ERR_CPU_RW_RK0                  (1 << 0)
 241 #define ERR_CPU_RW_RK1                  (1 << 1)
 242
 243
 244 #define DDR_RSV_MODE_ERR_MASK           (0x1f)
 245
 246 unsigned int check_last_dram_fatal_exception(void);
 247 unsigned int check_dram_fatal_exception(void);
 248 void set_err_code_for_storage_api(void);
 249 void dram_fatal_set_ta2_err(unsigned int chn, unsigned int err_code);
 250 void dram_fatal_set_gating_err(unsigned int chn, unsigned int err_code);
 251 void dram_fatal_set_cpu_rw_err(unsigned int err_code);
 252 void dram_fatal_set_stberr(unsigned int chn, unsigned int rk, unsigned int err_code);
 253
 254 void dram_fatal_backup_stberr(void);
 255 void dram_fatal_init_stberr(void);
 256 void dram_fatal_set_err(unsigned int err_code, unsigned int mask, unsigned int offset);
 257 #if 0
 258 unsigned int get_ch_num_by_auxadc(void);
 259 #endif
 260
 261 #define dram_fatal_set_cpu_rw_err(err_code)\
 262         do {\
 263                 dram_fatal_set_err(err_code, 0x3, OFFSET_CPU_RW_ERR);\
 264         } while(0)
 265
 266 #define dram_fatal_set_ddr_rsv_mode_err()\
 267         do {\
 268                 dram_fatal_set_err(0x1, 0x1, OFFSET_DDR_RSV_MODE_ERR);\
 269         } while(0)
 270
 271 #define dram_fatal_set_emi_dcs_err()\
 272         do {\
 273                 dram_fatal_set_err(0x1, 0x1, OFFSET_EMI_DCS_ERR);\
 274         } while(0)
 275
 276 #define dram_fatal_set_dvfsrc_err()\
 277         do {\
 278                 dram_fatal_set_err(0x1, 0x1, OFFSET_DVFSRC_ERR);\
 279         } while(0)
 280
 281 #define dram_fatal_set_drs_err()\
 282         do {\
 283                 dram_fatal_set_err(0x1, 0x1, OFFSET_DRS_ERR);\
 284         } while(0)
 285
 286 #define dram_fatal_set_ddr_rsv_mode_flow()\
 287         do {\
 288                 dram_fatal_set_err(0x1, 0x1, OFFSET_DDR_RSV_MODE_FLOW);\
 289         } while(0)
 290
 291 #endif
 292
 293 typedef enum {
 294         KSHU0 = 0,
 295         KSHU1,
 296         KSHU2,
 297         KSHU3,
 298         KSHU4,
 299         KSHU5,
 300         KSHU6,
 301         KSHU7,
 302         KSHU8,
 303         KSHU9,
 304 } DRAM_KSHU;
 305
 306 typedef enum {
 307         TYPE_VDRAM = 0,
 308         TYPE_VDDR1,
 309         TYPE_VDDR2,
 310         TYPE_VDDQ,
 311 } TYPE_VOLTAGE;
 312
 313 typedef enum {
 314         LEVEL_VB = 0,
 315         LEVEL_HV,
 316         LEVEL_NV,
 317         LEVEL_LV,
 318 } LEVEL_VOLTAGE;
 319
 320 //================================================
 321 //=============pmic related api for ETT HQA test ==============
 322 //================================================
 323 #if (__ETT__ || CFG_DRAM_LOG_TO_STORAGE)
 324 #define DRAM_HQA
 325 #endif
 326
 327 #define MAX_VCORE                       1193750
 328 #define MAX_VDRAM                       1300000
 329 #define MAX_VDDQ                        1300000
 330 #define MAX_VMDDR                       2000000
 331 #define MAX_VIO18                       1900000
 332
 333 #define UNIT_VCORE                      6250
 334 #define UNIT_VDRAM                      5000
 335 #define UNIT_VDDQ                       10000
 336 #define UNIT_VMDDR                      10000
 337 #define UNIT_VIO18                      10000
 338 #define UNIT_VIO18_STEP                 100000
 339
 340 #define HQA_VIO18_HV                    1950000
 341 #define HQA_VCORE_HV_LP4_KSHU0_PL       787500
 342 #define HQA_VCORE_HV_LP4_KSHU1_PL       737500
 343 #define HQA_VCORE_HV_LP4_KSHU2_PL       712500
 344 #define HQA_VCORE_HV_LP4_KSHU3_PL       712500
 345 #define HQA_VCORE_HV_LP4_KSHU4_PL       687500
 346 #define HQA_VCORE_HV_LP4_KSHU5_PL       687500
 347 #define HQA_VCORE_HV_LP4_KSHU6_PL       687500
 348 #define HQA_VCORE_HV_LP4_KSHU0_ETT      787500
 349 #define HQA_VCORE_HV_LP4_KSHU1_ETT      787500
 350 #define HQA_VCORE_HV_LP4_KSHU2_ETT      787500
 351 #define HQA_VCORE_HV_LP4_KSHU3_ETT      787500
 352 #define HQA_VCORE_HV_LP4_KSHU4_ETT      787500
 353 #define HQA_VCORE_HV_LP4_KSHU5_ETT      787500
 354 #define HQA_VCORE_HV_LP4_KSHU6_ETT      787500
 355 #define HQA_VDRAM_HV_LP4                1170000
 356 #define HQA_VDDQ_HV_LP4                 650000
 357 #define HQA_VMDDR_HV_LP4                790000
 358
 359 #if defined(MTK_AGING_FLAVOR_LOAD)
 360 #define HQA_VIO18_NV                    1730000
 361 #else
 362 #define HQA_VIO18_NV                    1800000
 363 #endif
 364 #define HQA_VCORE_NV_LP4_KSHU0_PL       750000
 365 #define HQA_VCORE_NV_LP4_KSHU1_PL       700000
 366 #define HQA_VCORE_NV_LP4_KSHU2_PL       675000
 367 #define HQA_VCORE_NV_LP4_KSHU3_PL       675000
 368 #define HQA_VCORE_NV_LP4_KSHU4_PL       650000
 369 #define HQA_VCORE_NV_LP4_KSHU5_PL       650000
 370 #define HQA_VCORE_NV_LP4_KSHU6_PL       650000
 371 #define HQA_VCORE_NV_LP4_KSHU0_ETT      750000
 372 #define HQA_VCORE_NV_LP4_KSHU1_ETT      700000
 373 #define HQA_VCORE_NV_LP4_KSHU2_ETT      675000
 374 #define HQA_VCORE_NV_LP4_KSHU3_ETT      675000
 375 #define HQA_VCORE_NV_LP4_KSHU4_ETT      650000
 376 #define HQA_VCORE_NV_LP4_KSHU5_ETT      650000
 377 #define HQA_VCORE_NV_LP4_KSHU6_ETT      650000
 378 #if defined(MTK_AGING_FLAVOR_LOAD)
 379 #define HQA_VDRAM_NV_LP4                1060000
 380 #define HQA_VDDQ_NV_LP4                 570000
 381 #define HQA_VMDDR_NV_LP4                710000
 382 #else
 383 #define HQA_VDRAM_NV_LP4                1125000
 384 #define HQA_VDDQ_NV_LP4                 600000
 385 #define HQA_VMDDR_NV_LP4                750000
 386 #endif
 387
 388 #define HQA_VIO18_LV                    1730000
 389 #define HQA_VCORE_LV_LP4_KSHU0_PL       712500
 390 #define HQA_VCORE_LV_LP4_KSHU1_PL       662500
 391 #define HQA_VCORE_LV_LP4_KSHU2_PL       637500
 392 #define HQA_VCORE_LV_LP4_KSHU3_PL       637500
 393 #define HQA_VCORE_LV_LP4_KSHU4_PL       612500
 394 #define HQA_VCORE_LV_LP4_KSHU5_PL       612500
 395 #define HQA_VCORE_LV_LP4_KSHU6_PL       612500
 396 #define HQA_VCORE_LV_LP4_KSHU0_ETT      712500
 397 #define HQA_VCORE_LV_LP4_KSHU1_ETT      612500
 398 #define HQA_VCORE_LV_LP4_KSHU2_ETT      568750
 399 #define HQA_VCORE_LV_LP4_KSHU3_ETT      568750
 400 #define HQA_VCORE_LV_LP4_KSHU4_ETT      518750
 401 #define HQA_VCORE_LV_LP4_KSHU5_ETT      518750
 402 #define HQA_VCORE_LV_LP4_KSHU6_ETT      518750
 403 #define HQA_VDRAM_LV_LP4                1060000
 404 #define HQA_VDDQ_LV_LP4                 570000
 405 #define HQA_VMDDR_LV_LP4                710000
 406
 407 #define  _SEL_PREFIX_SHU_PL(type,vol,dtype,shu)         HQA_##type##_##vol##_##dtype##_##shu##_PL
 408 #define  _SEL_PREFIX_SHU_ETT(type,vol,dtype,shu)        HQA_##type##_##vol##_##dtype##_##shu##_ETT
 409 #define  _SEL_PREFIX(type,vol,dtype)                    HQA_##type##_##vol##_##dtype
 410 #define  _SEL_VIO18(vol)                                HQA_VIO18_##vol
 411
 412 #define STD_VIO18                               _SEL_VIO18(NV)
 413 #define STD_VCORE(dtype,shu)    _SEL_PREFIX_SHU_PL(VCORE,NV,dtype,shu)
 414 #define STD_VDRAM(dtype)                _SEL_PREFIX(VDRAM,NV,dtype)
 415 #define STD_VDDQ                                _SEL_PREFIX(VDDQ,NV,LP4)
 416 #define STD_VMDDR                               _SEL_PREFIX(VMDDR,NV,LP4)
 417
 418 #if defined(MTK_AGING_FLAVOR_LOAD)
 419 #define DRAM_HQA
 420 #endif
 421
 422 #ifdef DRAM_HQA
 423 //#define HVCORE_HVDRAM
 424 #if defined(MTK_AGING_FLAVOR_LOAD)
 425 #define LVCORE_LVDRAM
 426 #else
 427 #define NVCORE_NVDRAM
 428 //#define LVCORE_LVDRAM
 429 //#define HVCORE_HVDRAM
 430 #endif
 431
 432 #if defined(HVCORE_HVDRAM)
 433         #define HQA_VCORE(dtype,shu)    _SEL_PREFIX_SHU_PL(VCORE,HV,dtype,shu)
 434         #define HQA_VDRAM(dtype)                _SEL_PREFIX(VDRAM,HV,dtype)
 435         #define HQA_VDDQ                                _SEL_PREFIX(VDDQ,HV,LP4)
 436         #define HQA_VMDDR                               _SEL_PREFIX(VMDDR,HV,LP4)
 437         #define HQA_VIO18                               _SEL_VIO18(HV)
 438 #elif defined(NVCORE_NVDRAM)
 439         #define HQA_VCORE(dtype,shu)    _SEL_PREFIX_SHU_PL(VCORE,NV,dtype,shu)
 440         #define HQA_VDRAM(dtype)                _SEL_PREFIX(VDRAM,NV,dtype)
 441         #define HQA_VDDQ                                _SEL_PREFIX(VDDQ,NV,LP4)
 442         #define HQA_VMDDR                               _SEL_PREFIX(VMDDR,NV,LP4)
 443         #define HQA_VIO18                               _SEL_VIO18(NV)
 444 #elif defined(LVCORE_LVDRAM)
 445         #define HQA_VCORE(dtype,shu)    _SEL_PREFIX_SHU_PL(VCORE,LV,dtype,shu)
 446         #define HQA_VDRAM(dtype)                _SEL_PREFIX(VDRAM,LV,dtype)
 447         #define HQA_VDDQ                                _SEL_PREFIX(VDDQ,LV,LP4)
 448         #define HQA_VMDDR                               _SEL_PREFIX(VMDDR,LV,LP4)
 449         #define HQA_VIO18                               _SEL_VIO18(LV)
 450 #elif defined(HVCORE_LVDRAM)
 451         #define HQA_VCORE(dtype,shu)    _SEL_PREFIX_SHU_PL(VCORE,HV,dtype,shu)
 452         #define HQA_VDRAM(dtype)                _SEL_PREFIX(VDRAM,LV,dtype)
 453         #define HQA_VDDQ                                _SEL_PREFIX(VDDQ,LV,LP4)
 454         #define HQA_VMDDR                               _SEL_PREFIX(VMDDR,LV,LP4)
 455         #define HQA_VIO18                               _SEL_VIO18(LV)
 456 #elif defined(LVCORE_HVDRAM)
 457         #define HQA_VCORE(dtype,shu)    _SEL_PREFIX_SHU_PL(VCORE,LV,dtype,shu)
 458         #define HQA_VDRAM(dtype)                _SEL_PREFIX(VDRAM,HV,dtype)
 459         #define HQA_VDDQ                                _SEL_PREFIX(VDDQ,HV,LP4)
 460         #define HQA_VMDDR                               _SEL_PREFIX(VMDDR,HV,LP4)
 461         #define HQA_VIO18                               _SEL_VIO18(HV)
 462 #else
 463         #error "Please set HQA voltage type"
 464 #endif
 465
 466 #define SEL_PREFIX_VCORE(dtype,shu)     HQA_VCORE(dtype,shu)
 467 #define SEL_PREFIX_VDRAM(dtype)         HQA_VDRAM(dtype)
 468 #define SEL_PREFIX_VDDQ                 HQA_VDDQ
 469 #define SEL_PREFIX_VMDDR                HQA_VMDDR
 470 #define SEL_VIO18                       HQA_VIO18
 471 #else
 472
 473 #if defined(MTK_AGING_FLAVOR_LOAD)
 474 //#define VCORE_BIN
 475 #endif
 476 #if !__ETT__
 477 //#define VCORE_BIN
 478 #endif
 479 #define SEL_PREFIX_VCORE(dtype,shu)     STD_VCORE(dtype,shu)
 480 #define SEL_PREFIX_VDRAM(dtype)         STD_VDRAM(dtype)
 481 #define SEL_PREFIX_VDDQ                 STD_VDDQ
 482 #define SEL_PREFIX_VMDDR                STD_VMDDR
 483 #define SEL_VIO18                       STD_VIO18
 484 #endif // #define DRAM_HQA
 485
 486 #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
 487
 488 #define PART_DRAM_DATA_SIZE     0x100000
 489
 490 #define DRAM_CALIBRATION_DATA_MAGIC     0x9502
 491
 492 typedef struct _DRAM_CALIBRATION_HEADER_T
 493 {
 494         u32     pl_version;
 495         u16     magic_number;
 496         u32     calib_err_code;
 497 } DRAM_CALIBRATION_HEADER_T;
 498
 499 typedef struct _DRAM_CALIBRATION_MRR_DATA_T
 500 {
 501         u16     checksum;
 502         u16 emi_checksum;
 503         DRAM_INFO_BY_MRR_T DramInfo;
 504 } DRAM_CALIBRATION_MRR_DATA_T;
 505
 506 typedef struct _DRAM_CALIBRATION_SHU_DATA_T
 507 {
 508         u16     checksum;
 509         u32     calib_err_code;
 510         SAVE_TIME_FOR_CALIBRATION_T     calibration_data;
 511 } DRAM_CALIBRATION_SHU_DATA_T;
 512
 513 typedef struct _DRAM_CALIBRATION_DATA_T
 514 {
 515         DRAM_CALIBRATION_HEADER_T header;
 516         DRAM_CALIBRATION_MRR_DATA_T mrr_info;
 517         DRAM_CALIBRATION_SHU_DATA_T     data[DRAM_DFS_SRAM_MAX];
 518 } DRAM_CALIBRATION_DATA_T;
 519
 520
 521 #define ERR_NULL_POINTER        (0x1)
 522 #define ERR_MAGIC_NUMBER        (0x2)
 523 #define ERR_CHECKSUM            (0x3)
 524 #define ERR_PL_UPDATED          (0x4)
 525 #define ERR_BLKDEV_NOT_FOUND    (0x5)
 526 #define ERR_BLKDEV_READ_FAIL    (0x6)
 527 #define ERR_BLKDEV_WRITE_FAIL   (0x7)
 528 #define ERR_BLKDEV_NO_PART      (0x8)
 529
 530 #define ERR_DATA_FORMATTED_OFFSET       (12)
 531
 532 typedef enum {
 533         DRAM_STORAGE_API_READ = 0,
 534         DRAM_STORAGE_API_WRITE,
 535         DRAM_STORAGE_API_CLEAN,
 536 } DRAM_STORAGE_API_TPYE;
 537
 538 extern u32 g_dram_storage_api_err_code;
 539 #define SET_DRAM_STORAGE_API_ERR(err_type, api_type) \
 540 do {\
 541         g_dram_storage_api_err_code |= (err_type << (api_type * 4));\
 542 } while(0)
 543
 544 #define SET_DATA_FORMATTED_STORAGE_API_ERR() \
 545 do {\
 546         g_dram_storage_api_err_code |= (1 << ERR_DATA_FORMATTED_OFFSET);\
 547 } while(0)
 548
 549 int read_offline_dram_calibration_data(DRAM_DFS_SRAM_SHU_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData);
 550 int write_offline_dram_calibration_data(DRAM_DFS_SRAM_SHU_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData);
 551 int clean_dram_calibration_data(void);
 552
 553 void dram_fatal_exception_detection_start(void);
 554 void dram_fatal_exception_detection_end(void);
 555
 556 #define CBT_VREF_OFFSET                 2
 557 #define WRITE_LEVELING_OFFSET           5
 558 #define GATING_START_OFFSET             0
 559 #define GATING_PASS_WIN_OFFSET          3
 560 #define RX_WIN_PERBIT_OFFSET            5
 561 #define RX_WIN_PERBIT_VREF_OFFSET       4
 562 #define TX_WIN_PERBIT_OFFSET            5
 563 #define TX_WIN_PERBIT_VREF_OFFSET       4
 564 #define RX_DATLAT_OFFSET                1
 565 #define RX_WIN_HIGH_SPEED_TH            10
 566 #define RX_WIN_LOW_SPEED_TH             100
 567 #define TX_WIN_TH                       12
 568
 569 #endif
 570
 571 #if defined(SLT)
 572
 573 #define SLT_ERR_NO_DATA         (-1)
 574 #define SLT_ERR_NO_DEV          (-2)
 575 #define SLT_ERR_NO_ADDR         (-3)
 576 #define SLT_ERR_WRITE_FAIL      (-4)
 577 #define SLT_ERR_READ_FAIL       (-5)
 578
 579 typedef struct _DRAM_SLT_HEADER_T
 580 {
 581         u32 pl_version;
 582         int stage_status;
 583 } DRAM_SLT_HEADER_T;
 584
 585 typedef struct _DRAM_SLT_DATA_T
 586 {
 587         DRAM_SLT_HEADER_T header;
 588         u32 test_result[10];
 589 } DRAM_SLT_DATA_T;
 590
 591 int read_slt_data(DRAM_SLT_DATA_T *data);
 592 int write_slt_data(DRAM_SLT_DATA_T *data);
 593 int clean_slt_data(void);
 594
 595 #endif
 596
 597 unsigned long long get_dram_size(void);
 598
 599 typedef struct {
 600         unsigned long long full_sys_addr;
 601         unsigned int addr;
 602         unsigned int row;
 603         unsigned int col;
 604         unsigned char ch;
 605         unsigned char rk;
 606         unsigned char bk;
 607         unsigned char dummy;
 608 } dram_addr_t;
 609
 610 unsigned int get_dramc_addr(dram_addr_t *dram_addr, unsigned int offset);
 611 unsigned int get_dummy_read_addr(dram_addr_t *dram_addr);
 612 unsigned int is_discrete_lpddr4(void);
 613 unsigned int DRAM_MRR(int MRR_num);
 614
 615 void dram_auto_detection(void);
 616
 617 int mt_get_freq_setting(DRAMC_CTX_T *p);
 618 unsigned int dramc_get_vmdd_voltage(unsigned int ddr_type);
 619 unsigned int dramc_get_vmddq_voltage(unsigned int ddr_type);
 620 unsigned int dramc_set_vmdd_voltage(unsigned int ddr_type, unsigned int vdram);
 621 unsigned int dramc_set_vmddq_voltage(unsigned int ddr_type, unsigned int vddq);
 622
 623 void release_dram(void);
 624
 625 #endif /* __DRAMC_TOP_H__ */