util/inteltool/gpio_names/cannonlake_lp.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef GPIO_NAMES_CANNONLAKE_LP
   4 #define GPIO_NAMES_CANNONLAKE_LP
   5
   6 #include "gpio_groups.h"
   7
   8 const char *const cannonlake_pch_lp_group_a_names[] = {
   9         "GPP_A0",               "RCIN#",                "TIME_SYNC1",   "n/a",
  10         "GPP_A1",               "LAD0",                 "ESPI_IO0",     "n/a",
  11         "GPP_A2",               "LAD1",                 "ESPI_IO1",     "n/a",
  12         "GPP_A3",               "LAD2",                 "ESPI_IO2",     "n/a",
  13         "GPP_A4",               "LAD3",                 "ESPI_IO3",     "n/a",
  14         "GPP_A5",               "LFRAME#",              "ESPI_CS0#",    "n/a",
  15         "GPP_A6",               "SERIRQ",               "n/a",          "n/a",
  16         "GPP_A7",               "PIRQA#",               "GSPI0_CS1#",   "n/a",
  17         "GPP_A8",               "CLKRUN#",              "n/a",          "n/a",
  18         "GPP_A9",               "CLKOUT_LPC0",          "ESPI_CLK",     "n/a",
  19         "GPP_A10",              "CLKOUT_LPC1",          "n/a",          "n/a",
  20         "GPP_A11",              "PME#",                 "GSPI1_CS1#",   "SD_VDD2_PWR_EN#",
  21         "GPP_A12",              "BM_BUSY#",             "ISH_GP6",      "SX_EXIT_HOLDOFF#",
  22         "GPP_A13",              "SUSWARN#/SUSPWRDNACK", "n/a",          "n/a",
  23         "GPP_A14",              "SUS_STAT#",            "ESPI_RESET#",  "n/a",
  24         "GPP_A15",              "SUSACK#",              "n/a",          "n/a",
  25         "GPP_A16",              "SD_1P8_SEL",           "n/a",          "n/a",
  26         "GPP_A17",              "SD_VDD1_PWR_EN#",      "ISH_GP7",      "n/a",
  27         "GPP_A18",              "ISH_GP0",              "n/a",          "n/a",
  28         "GPP_A19",              "ISH_GP1",              "n/a",          "n/a",
  29         "GPP_A20",              "ISH_GP2",              "n/a",          "n/a",
  30         "GPP_A21",              "ISH_GP3",              "n/a",          "n/a",
  31         "GPP_A22",              "ISH_GP4",              "n/a",          "n/a",
  32         "GPP_A23",              "ISH_GP5",              "n/a",          "n/a",
  33         "ESPI_CLK_LOOPBK",      "ESPI_CLK_LOOPBK",      "n/a",          "n/a",
  34 };
  35
  36 const struct gpio_group cannonlake_pch_lp_group_a = {
  37         .display        = "------- GPIO Group GPP_A -------",
  38         .pad_count      = ARRAY_SIZE(cannonlake_pch_lp_group_a_names) / 4,
  39         .func_count     = 4,
  40         .pad_names      = cannonlake_pch_lp_group_a_names,
  41 };
  42
  43 const char *const cannonlake_pch_lp_group_b_names[] = {
  44         "GPP_B0",               "CORE_VID0",            "n/a",
  45         "GPP_B1",               "CORE_VID1",            "n/a",
  46         "GPP_B2",               "VRALERT#",             "n/a",
  47         "GPP_B3",               "CPU_GP2",              "n/a",
  48         "GPP_B4",               "CPU_GP3",              "n/a",
  49         "GPP_B5",               "SRCCLKREQ0#",          "n/a",
  50         "GPP_B6",               "SRCCLKREQ1#",          "n/a",
  51         "GPP_B7",               "SRCCLKREQ2#",          "n/a",
  52         "GPP_B8",               "SRCCLKREQ3#",          "n/a",
  53         "GPP_B9",               "SRCCLKREQ4#",          "n/a",
  54         "GPP_B10",              "SRCCLKREQ5#",          "n/a",
  55         "GPP_B11",              "EXT_PWR_GATE#",        "n/a",
  56         "GPP_B12",              "SLP_S0#",              "n/a",
  57         "GPP_B13",              "PLTRST#",              "n/a",
  58         "GPP_B14",              "SPKR",                 "n/a",
  59         "GPP_B15",              "GSPI0_CS0#",           "n/a",
  60         "GPP_B16",              "GSPI0_CLK",            "n/a",
  61         "GPP_B17",              "GSPI0_MISO",           "n/a",
  62         "GPP_B18",              "GSPI0_MOSI",           "n/a",
  63         "GPP_B19",              "GSPI1_CS0#",           "n/a",
  64         "GPP_B20",              "GSPI1_CLK",            "n/a",
  65         "GPP_B21",              "GSPI1_MISO",           "n/a",
  66         "GPP_B22",              "GSPI1_MOSI",           "n/a",
  67         "GPP_B23",              "SML1ALERT#",           "PCHHOT#",
  68         "GSPI0_CLK_LOOPBK",     "GSPI0_CLK_LOOPBK",     "n/a",
  69         "GSPI1_CLK_LOOPBK",     "GSPI1_CLK_LOOPBK",     "n/a",
  70 };
  71
  72 const struct gpio_group cannonlake_pch_lp_group_b = {
  73         .display        = "------- GPIO Group GPP_B -------",
  74         .pad_count      = ARRAY_SIZE(cannonlake_pch_lp_group_b_names) / 3,
  75         .func_count     = 3,
  76         .pad_names      = cannonlake_pch_lp_group_b_names,
  77 };
  78
  79 const char *const cannonlake_pch_lp_group_c_names[] = {
  80         "GPP_C0",       "SMBCLK",       "n/a",                  "n/a",
  81         "GPP_C1",       "SMBDATA",      "n/a",                  "n/a",
  82         "GPP_C2",       "SMBALERT#",    "n/a",                  "n/a",
  83         "GPP_C3",       "SML0CLK",      "n/a",                  "n/a",
  84         "GPP_C4",       "SML0DATA",     "n/a",                  "n/a",
  85         "GPP_C5",       "SML0ALERT#",   "n/a",                  "n/a",
  86         "GPP_C6",       "SML1CLK",      "n/a",                  "n/a",
  87         "GPP_C7",       "SML1DATA",     "n/a",                  "n/a",
  88         "GPP_C8",       "UART0_RXD",    "n/a",                  "n/a",
  89         "GPP_C9",       "UART0_TXD",    "n/a",                  "n/a",
  90         "GPP_C10",      "UART0_RTS#",   "n/a",                  "n/a",
  91         "GPP_C11",      "UART0_CTS#",   "n/a",                  "n/a",
  92         "GPP_C12",      "UART1_RXD",    "ISH_UART1_RXD",        "CNV_MFUART1_RXD",
  93         "GPP_C13",      "UART1_TXD",    "ISH_UART1_TXD",        "CNV_MFUART1_TXD",
  94         "GPP_C14",      "UART1_RTS#",   "ISH_UART1_RTS#",       "CNV_MFUART1_RTS",
  95         "GPP_C15",      "UART1_CTS#",   "ISH_UART1_CTS#",       "CNV_MFUART1_CTS",
  96         "GPP_C16",      "I2C0_SDA",     "n/a",                  "n/a",
  97         "GPP_C17",      "I2C0_SCL",     "n/a",                  "n/a",
  98         "GPP_C18",      "I2C1_SDA",     "n/a",                  "n/a",
  99         "GPP_C19",      "I2C1_SCL",     "n/a",                  "n/a",
 100         "GPP_C20",      "UART2_RXD",    "n/a",                  "n/a",
 101         "GPP_C21",      "UART2_TXD",    "n/a",                  "n/a",
 102         "GPP_C22",      "UART2_RTS#",   "n/a",                  "n/a",
 103         "GPP_C23",      "UART2_CTS#",   "n/a",                  "n/a",
 104 };
 105
 106 const struct gpio_group cannonlake_pch_lp_group_c = {
 107         .display        = "------- GPIO Group GPP_C -------",
 108         .pad_count      = ARRAY_SIZE(cannonlake_pch_lp_group_c_names) / 4,
 109         .func_count     = 4,
 110         .pad_names      = cannonlake_pch_lp_group_c_names,
 111 };
 112
 113 const char *const cannonlake_pch_lp_group_d_names[] = {
 114         "GPP_D0",               "SPI1_CS#",             "BK0",          "SBK0",
 115         "GPP_D1",               "SPI1_CLK",             "BK1",          "SBK1",
 116         "GPP_D2",               "SPI1_MISO",            "BK2",          "SBK2",
 117         "GPP_D3",               "SPI1_MOSI",            "BK3",          "SBK3",
 118         "GPP_D4",               "IMGCLKOUT0",           "BK4",          "SBK4",
 119         "GPP_D5",               "ISH_I2C0_SDA",         "n/a",          "n/a",
 120         "GPP_D6",               "ISH_I2C0_SCL",         "n/a",          "n/a",
 121         "GPP_D7",               "ISH_I2C1_SDA",         "n/a",          "n/a",
 122         "GPP_D8",               "ISH_I2C1_SCL",         "n/a",          "n/a",
 123         "GPP_D9",               "ISH_SPI_CS#",          "n/a",          "GSPI2_CS0#",
 124         "GPP_D10",              "ISH_SPI_CLK",          "n/a",          "GSPI2_CLK",
 125         "GPP_D11",              "ISH_SPI_MISO",         "n/a",          "GSPI2_MISO",
 126         "GPP_D12",              "ISH_SPI_MOSI",         "n/a",          "GSPI2_MOSI",
 127         "GPP_D13",              "ISH_UART0_RXD",        "SML0BDATA",    "I2C4B_SDA",
 128         "GPP_D14",              "ISH_UART0_TXD",        "SML0BCLK",     "I2C4B_SCL",
 129         "GPP_D15",              "ISH_UART0_RTS#",       "GSPI2_CS1#",   "n/a",
 130         "GPP_D16",              "ISH_UART0_CTS#",       "SML0BALERT",   "n/a",
 131         "GPP_D17",              "DMIC_CLK1",            "SNDW3_CLK",    "n/a",
 132         "GPP_D18",              "DMIC_DATA1",           "SNDW3_DATA",   "n/a",
 133         "GPP_D19",              "DMIC_CLK0",            "SNDW4_CLK",    "n/a",
 134         "GPP_D20",              "DMIC_DATA0",           "SNDW4_DATA",   "n/a",
 135         "GPP_D21",              "SPI1_IO2",             "n/a",          "n/a",
 136         "GPP_D22",              "SPI1_IO3",             "n/a",          "n/a",
 137         "GPP_D23",              "I2S_MCLK",             "n/a",          "n/a",
 138         "GSPI2_CLK_LOOPBK",     "GSPI2_CLK_LOOPBK",     "n/a",          "n/a",
 139 };
 140
 141 const struct gpio_group cannonlake_pch_lp_group_d = {
 142         .display        = "------- GPIO Group GPP_D -------",
 143         .pad_count      = ARRAY_SIZE(cannonlake_pch_lp_group_d_names) / 4,
 144         .func_count     = 4,
 145         .pad_names      = cannonlake_pch_lp_group_d_names,
 146 };
 147
 148 const char *const cannonlake_pch_lp_group_e_names[] = {
 149         "GPP_E0",       "SATAXPCIE0",           "SATAGP0",      "n/a",
 150         "GPP_E1",       "SATAXPCIE1",           "n/a",          "n/a",
 151         "GPP_E2",       "SATAXPCIE2",           "n/a",          "n/a",
 152         "GPP_E3",       "CPU_GP0",              "n/a",          "n/a",
 153         "GPP_E4",       "SATA_DEVSLP0",         "n/a",          "n/a",
 154         "GPP_E5",       "SATA_DEVSLP1",         "n/a",          "n/a",
 155         "GPP_E6",       "SATA_DEVSLP2",         "n/a",          "n/a",
 156         "GPP_E7",       "CPU_GP1",              "n/a",          "n/a",
 157         "GPP_E8",       "SATALED#",             "n/a",          "n/a",
 158         "GPP_E9",       "USB2_OC0#",            "n/a",          "n/a",
 159         "GPP_E10",      "USB2_OC1#",            "n/a",          "n/a",
 160         "GPP_E11",      "USB2_OC2#",            "n/a",          "n/a",
 161         "GPP_E12",      "USB2_OC3#",            "n/a",          "n/a",
 162         "GPP_E13",      "DDPB_HPD0",            "DISP_MISC0",   "n/a",
 163         "GPP_E14",      "DDPC_HPD1",            "DISP_MISC1",   "n/a",
 164         "GPP_E15",      "DDPD_HPD2",            "DISP_MISC2",   "n/a",
 165         "GPP_E16",      "n/a",                  "DISP_MISC3",   "n/a",
 166         "GPP_E17",      "EDP_HPD",              "DISP_MISC4",   "n/a",
 167         "GPP_E18",      "DPPB_CTRLCLK",         "n/a",          "CNV_BT_HOST_WAKE#",
 168         "GPP_E19",      "DPPB_CTRLDATA",        "n/a",          "CNV_BT_IF_SELECT",
 169         "GPP_E20",      "DPPC_CTRLCLK",         "n/a",          "n/a",
 170         "GPP_E21",      "DPPC_CTRLDATA",        "n/a",          "n/a",
 171         "GPP_E22",      "DPPD_CTRLCLK",         "n/a",          "n/a",
 172         "GPP_E23",      "DPPD_CTRLDATA",        "n/a",          "n/a",
 173 };
 174
 175 const struct gpio_group cannonlake_pch_lp_group_e = {
 176         .display        = "------- GPIO Group GPP_E -------",
 177         .pad_count      = ARRAY_SIZE(cannonlake_pch_lp_group_e_names) / 4,
 178         .func_count     = 4,
 179         .pad_names      = cannonlake_pch_lp_group_e_names,
 180 };
 181
 182 const char *const cannonlake_pch_lp_group_f_names[] = {
 183         "GPP_F0",       "CNV_PA_BLANKING",      "n/a",
 184         "GPP_F1",       "n/a",                  "n/a",
 185         "GPP_F2",       "n/a",                  "n/a",
 186         "GPP_F3",       "n/a",                  "n/a",
 187         "GPP_F4",       "CNV_BRI_DT",           "UART0_RTS#",
 188         "GPP_F5",       "CNV_BRI_RSP",          "UART0_RXD",
 189         "GPP_F6",       "CNV_RGI_DT",           "UART0_TXD",
 190         "GPP_F7",       "CNV_RGI_RSP",          "UART0_CTS#",
 191         "GPP_F8",       "CNV_MFUART2_RXD",      "n/a",
 192         "GPP_F9",       "CNV_MFUART2_TXD",      "n/a",
 193         "GPP_F10",      "n/a",                  "n/a",
 194         "GPP_F11",      "EMMC_CMD",             "n/a",
 195         "GPP_F12",      "EMMC_DATA0",           "n/a",
 196         "GPP_F13",      "EMMC_DATA1",           "n/a",
 197         "GPP_F14",      "EMMC_DATA2",           "n/a",
 198         "GPP_F15",      "EMMC_DATA3",           "n/a",
 199         "GPP_F16",      "EMMC_DATA4",           "n/a",
 200         "GPP_F17",      "EMMC_DATA5",           "n/a",
 201         "GPP_F18",      "EMMC_DATA6",           "n/a",
 202         "GPP_F19",      "EMMC_DATA7",           "n/a",
 203         "GPP_F20",      "EMMC_RCLK",            "n/a",
 204         "GPP_F21",      "EMMC_CLK",             "n/a",
 205         "GPP_F22",      "EMMC_RESET#",          "n/a",
 206         "GPP_F23",      "A4WP_PRESENT",         "n/a",
 207 };
 208
 209 const struct gpio_group cannonlake_pch_lp_group_f = {
 210         .display        = "------- GPIO Group GPP_F -------",
 211         .pad_count      = ARRAY_SIZE(cannonlake_pch_lp_group_f_names) / 3,
 212         .func_count     = 3,
 213         .pad_names      = cannonlake_pch_lp_group_f_names,
 214 };
 215
 216 const char *const cannonlake_pch_lp_group_g_names[] = {
 217         "GPP_G0",       "SD_CMD",
 218         "GPP_G1",       "SD_DATA0",
 219         "GPP_G2",       "SD_DATA1",
 220         "GPP_G3",       "SD_DATA2",
 221         "GPP_G4",       "SD_DATA3",
 222         "GPP_G5",       "SD3_CD#",
 223         "GPP_G6",       "SD3_CLK",
 224         "GPP_G7",       "SD3_WP",
 225 };
 226
 227 const struct gpio_group cannonlake_pch_lp_group_g = {
 228         .display        = "------- GPIO Group GPP_G -------",
 229         .pad_count      = ARRAY_SIZE(cannonlake_pch_lp_group_g_names) / 2,
 230         .func_count     = 2,
 231         .pad_names      = cannonlake_pch_lp_group_g_names,
 232 };
 233
 234 const char *const cannonlake_pch_lp_group_h_names[] = {
 235         "GPP_H0",       "I2S2_SCLK",            "CNV_BT_I2S_SCLK",      "n/a",
 236         "GPP_H1",       "I2S2_SFRM",            "CNV_BT_I2S_BCLK",      "CNV_RF_RESET#",
 237         "GPP_H2",       "I2S2_TXD",             "CNV_BT_I2S_SDI",       "MODEM_CLKREQ",
 238         "GPP_H3",       "I2S2_RXD",             "CNV_BT_I2S_SDO",       "n/a",
 239         "GPP_H4",       "I2C2_SDA",             "n/a",                  "n/a",
 240         "GPP_H5",       "I2C2_SCL",             "n/a",                  "n/a",
 241         "GPP_H6",       "I2C3_SDA",             "n/a",                  "n/a",
 242         "GPP_H7",       "I2C3_SCL",             "n/a",                  "n/a",
 243         "GPP_H8",       "I2C4_SDA",             "n/a",                  "n/a",
 244         "GPP_H9",       "I2C4_SCL",             "n/a",                  "n/a",
 245         "GPP_H10",      "I2C5_SDA",             "ISH_I2C2_SDA",         "n/a",
 246         "GPP_H11",      "I2C5_SCL",             "ISH_I2C2_SCL",         "n/a",
 247         "GPP_H12",      "M2_SKT2_CFG0",         "n/a",                  "n/a",
 248         "GPP_H13",      "M2_SKT2_CFG1",         "n/a",                  "n/a",
 249         "GPP_H14",      "M2_SKT2_CFG2",         "n/a",                  "n/a",
 250         "GPP_H15",      "M2_SKT2_CFG3",         "n/a",                  "n/a",
 251         "GPP_H16",      "n/a",                  "n/a",                  "n/a",
 252         "GPP_H17",      "n/a",                  "n/a",                  "n/a",
 253         "GPP_H18",      "CPU_C10_GATE#",        "n/a",                  "n/a",
 254         "GPP_H19",      "TIME_SYNC0",           "n/a",                  "n/a",
 255         "GPP_H20",      "IMGCLKOUT1",           "n/a",                  "n/a",
 256         "GPP_H21",      "n/a",                  "n/a",                  "n/a",
 257         "GPP_H22",      "n/a",                  "n/a",                  "n/a",
 258         "GPP_H23",      "n/a",                  "n/a",                  "n/a",
 259 };
 260
 261 const struct gpio_group cannonlake_pch_lp_group_h = {
 262         .display        = "------- GPIO Group GPP_H -------",
 263         .pad_count      = ARRAY_SIZE(cannonlake_pch_lp_group_h_names) / 4,
 264         .func_count     = 4,
 265         .pad_names      = cannonlake_pch_lp_group_h_names,
 266 };
 267
 268 const char *const cannonlake_pch_lp_group_gpd_names[] = {
 269         "GPD0",         "BATLOW#",
 270         "GPD1",         "ACPRESENT",
 271         "GPD2",         "LAN_WAKE#",
 272         "GPD3",         "PRWBTN#",
 273         "GPD4",         "SLP_S3#",
 274         "GPD5",         "SLP_S4#",
 275         "GPD6",         "SLP_A#",
 276         "GPD7",         "n/a",
 277         "GPD8",         "SUSCLK",
 278         "GPD9",         "SLP_WLAN#",
 279         "GPD10",        "SLP_S5#",
 280         "GPD11",        "LANPHYPC",
 281         "SLP_LAN_B",    "SLP_LAN#",
 282         "SLP_SUS_B",    "SLP_SUS#",
 283         "WAKE_B",       "WAKE#",
 284         "DRAM_RESET_B", "DRAM_RESET#",
 285 };
 286
 287 const struct gpio_group cannonlake_pch_lp_group_gpd = {
 288         .display        = "------- GPIO Group GPD -------",
 289         .pad_count      = ARRAY_SIZE(cannonlake_pch_lp_group_gpd_names) / 2,
 290         .func_count     = 2,
 291         .pad_names      = cannonlake_pch_lp_group_gpd_names,
 292 };
 293
 294 const char *const cannonlake_pch_lp_group_vgpio_names[] = {
 295         "CNV_BTEN",                     "n/a",          "n/a",          "n/a",
 296         "CNV_GNEN",                     "n/a",          "n/a",          "n/a",
 297         "CNV_WFEN",                     "n/a",          "n/a",          "n/a",
 298         "CNV_WCEN",                     "n/a",          "n/a",          "n/a",
 299         "CNV_BT_HOST_WAKE_B",           "n/a",          "n/a",          "n/a",
 300         "CNV_BT_IF_SELECT",             "n/a",          "n/a",          "n/a",
 301         "vCNV_BT_UART_TXD",             "ISH UART0",    "SIo UART2",    "n/a",
 302         "vCNV_BT_UART_RXD",             "ISH UART0",    "SIo UART2",    "n/a",
 303         "vCNV_BT_UART_CTS_B",           "ISH UART0",    "SIo UART2",    "n/a",
 304         "vCNV_BT_UART_RTS_B",           "ISH UART0",    "SIo UART2",    "n/a",
 305         "vCNV_MFUART1_TXD",             "ISH UART0",    "SIo UART2",    "n/a",
 306         "vCNV_MFUART1_RXD",             "ISH UART0",    "SIo UART2",    "n/a",
 307         "vCNV_MFUART1_CTS_B",           "ISH UART0",    "SIo UART2",    "n/a",
 308         "vCNV_MFUART1_RTS_B",           "ISH UART0",    "SIo UART2",    "n/a",
 309         "vCNV_GNSS_UART_TXD",           "n/a",          "n/a",          "n/a",
 310         "vCNV_GNSS_UART_RXD",           "n/a",          "n/a",          "n/a",
 311         "vCNV_GNSS_UART_CTS_B",         "n/a",          "n/a",          "n/a",
 312         "vCNV_GNSS_UART_RTS_B",         "n/a",          "n/a",          "n/a",
 313         "vUART0_TXD",                   "mapped",       "n/a",          "n/a",
 314         "vUART0_RXD",                   "mapped",       "n/a",          "n/a",
 315         "vUART0_CTS_B",                 "mapped",       "n/a",          "n/a",
 316         "vUART0_RTS_B",                 "mapped",       "n/a",          "n/a",
 317         "vISH_UART0_TXD",               "mapped",       "n/a",          "n/a",
 318         "vISH_UART0_RXD",               "mapped",       "n/a",          "n/a",
 319         "vISH_UART0_CTS_B",             "mapped",       "n/a",          "n/a",
 320         "vISH_UART0_RTS_B",             "mapped",       "n/a",          "n/a",
 321         "vISH_UART1_TXD",               "mapped",       "n/a",          "n/a",
 322         "vISH_UART1_RXD",               "mapped",       "n/a",          "n/a",
 323         "vISH_UART1_CTS_B",             "mapped",       "n/a",          "n/a",
 324         "vISH_UART1_RTS_B",             "mapped",       "n/a",          "n/a",
 325         "vCNV_BT_I2S_BCLK",             "SSP0",         "SSP1",         "SSP2",
 326         "vCNV_BT_I2S_WS_SYNC",          "SSP0",         "SSP1",         "SSP2",
 327         "vCNV_BT_I2S_SDO",              "SSP0",         "SSP1",         "SSP2",
 328         "vCNV_BT_I2S_SDI",              "SSP0",         "SSP1",         "SSP2",
 329         "vSSP2_SCLK",                   "mapped",       "n/a",          "n/a",
 330         "vSSP2_SFRM",                   "mapped",       "n/a",          "n/a",
 331         "vSSP2_TXD",                    "mapped",       "n/a",          "n/a",
 332         "vSSP2_RXD",                    "n/a",          "n/a",          "n/a",
 333         "vCNV_GNSS_HOST_WAKE_B",        "n/a",          "n/a",          "n/a",
 334         "vSD3_CD_B",                    "n/a",          "n/a",          "n/a",
 335 };
 336
 337 const struct gpio_group cannonlake_pch_lp_group_vgpio = {
 338         .display        = "------- GPIO Group VGPIO -------",
 339         .pad_count      = ARRAY_SIZE(cannonlake_pch_lp_group_vgpio_names) / 4,
 340         .func_count     = 4,
 341         .pad_names      = cannonlake_pch_lp_group_vgpio_names,
 342 };
 343
 344 const char *const cannonlake_pch_lp_group_spi_names[] = {
 345         "SPI0_IO_2",            "SPI0_IO_2",
 346         "SPI0_IO_3",            "SPI0_IO_3",
 347         "SPI0_MISO",            "SPI0_MISO",
 348         "SPI0_MOSI",            "SPI0_MOSI",
 349         "SPI0_CS2_B",           "SPI0_CS2#",
 350         "SPI0_CS0_B",           "SPI0_CS0#",
 351         "SPI0_CS1_B",           "SPI0_CS1#",
 352         "SPI0_CLK",             "SPI0_CLK",
 353         "SPI0_CLK_LOOPBK",      "SPI0_CLK_LOOPBK",
 354 };
 355
 356 const struct gpio_group cannonlake_pch_lp_group_spi = {
 357         .display        = "------- GPIO Group SPI -------",
 358         .pad_count      = ARRAY_SIZE(cannonlake_pch_lp_group_spi_names) / 2,
 359         .func_count     = 2,
 360         .pad_names      = cannonlake_pch_lp_group_spi_names,
 361 };
 362
 363 const char *const cannonlake_pch_lp_group_aza_names[] = {
 364         "HDA_BCLK",     "HDA_BCLK",     "I2S0_SCLK",    "n/a",
 365         "HDA_RST_B",    "HDA_RST#",     "I2S1_SCLK",    "SNDW1_CLK",
 366         "HDA_SYNC",     "HDA_SYNC",     "I2S0_SFRM",    "n/a",
 367         "HDA_SDO",      "HDA_SDO",      "I2S0_TXD",     "n/a",
 368         "HDA_SDI0",     "HDA_SDI0",     "I2S0_RXD",     "n/a",
 369         "HDA_SDI1",     "HDA_SDI1",     "I2S1_RXD",     "SNDW1_DATA",
 370         "I2S1_SFRM",    "I2S1_SFRM",    "SNDW2_CLK",    "n/a",
 371         "I2S1_TXD",     "I2S1_TXD",     "SNDW2_DATA",   "n/a",
 372 };
 373
 374 const struct gpio_group cannonlake_pch_lp_group_aza = {
 375         .display        = "------- GPIO Group AZA -------",
 376         .pad_count      = ARRAY_SIZE(cannonlake_pch_lp_group_aza_names) / 4,
 377         .func_count     = 4,
 378         .pad_names      = cannonlake_pch_lp_group_aza_names,
 379 };
 380
 381 const char *const cannonlake_pch_lp_group_cpu_names[] = {
 382         "HDACPU_SDI",   "HDACPU_SDI",
 383         "HDACPU_SDO",   "HDACPU_SDO",
 384         "HDACPU_SCLK",  "HDACPU_SCLK",
 385         "PM_SYNC",      "PM_SYNC",
 386         "PECI",         "PECI",
 387         "CPUPWRGD",     "CPUPWRGD",
 388         "THRMTRIP_B",   "THRMTRIP#",
 389         "PLTRST_CPU_B", "PLTRST_CPU#",
 390         "PM_DOWN",      "PM_DOWN",
 391         "TRIGGER_IN",   "TRIGGER_IN",
 392         "TRIGGER_OUT",  "TRIGGER_OUT",
 393 };
 394
 395 const struct gpio_group cannonlake_pch_lp_group_cpu = {
 396         .display        = "------- GPIO Group CPU -------",
 397         .pad_count      = ARRAY_SIZE(cannonlake_pch_lp_group_cpu_names) / 2,
 398         .func_count     = 2,
 399         .pad_names      = cannonlake_pch_lp_group_cpu_names,
 400 };
 401
 402 const char *const cannonlake_pch_lp_group_jtag_names[] = {
 403         "PCH_TDO",      "PCH_TDO",
 404         "PCH_JTAGX",    "PCH_JTAGX",
 405         "PROC_PRDY_B",  "PROC_PRDY#",
 406         "PROC_PREQ_B",  "PROC_PREQ#",
 407         "CPU_TRST_B",   "CPU_TRST#",
 408         "PCH_TDI",      "PCH_TDI",
 409         "PCH_TMS",      "PCH_TMS",
 410         "PCH_TCK",      "PCH_TCK",
 411         "ITP_PMODE",    "ITP_PMODE",
 412 };
 413
 414 const struct gpio_group cannonlake_pch_lp_group_jtag = {
 415         .display        = "------- GPIO Group JTAG -------",
 416         .pad_count      = ARRAY_SIZE(cannonlake_pch_lp_group_jtag_names) / 2,
 417         .func_count     = 2,
 418         .pad_names      = cannonlake_pch_lp_group_jtag_names,
 419 };
 420
 421 const char *const cannonlake_pch_lp_group_hvmos_names[] = {
 422         "EDP_VDDEN",    "EDP_VDDEN",
 423         "EDP_BKLTEN",   "EDP_BKLTEN",
 424         "EDP_BKLTCTL",  "EDP_BKLTCTL",
 425         "SYS_PWROK",    "SYS_PWROK",
 426         "SYS_RESET_B",  "SYS_RESET#",
 427         "CL_RST_B",     "CL_RST#",
 428 };
 429
 430 const struct gpio_group cannonlake_pch_lp_group_hvmos = {
 431         .display        = "------- GPIO Group HVMOS -------",
 432         .pad_count      = ARRAY_SIZE(cannonlake_pch_lp_group_hvmos_names) / 2,
 433         .func_count     = 2,
 434         .pad_names      = cannonlake_pch_lp_group_hvmos_names,
 435 };
 436
 437 const struct gpio_group *const cannonlake_pch_lp_community_0_groups[] = {
 438         &cannonlake_pch_lp_group_a,
 439         &cannonlake_pch_lp_group_b,
 440         &cannonlake_pch_lp_group_g,
 441         &cannonlake_pch_lp_group_spi,
 442 };
 443
 444 const struct gpio_community cannonlake_pch_lp_community_0 = {
 445         .name           = "------- GPIO Community 0 -------",
 446         .pcr_port_id    = 0x6e,
 447         .group_count    = ARRAY_SIZE(cannonlake_pch_lp_community_0_groups),
 448         .groups         = cannonlake_pch_lp_community_0_groups,
 449 };
 450
 451 const struct gpio_group *const cannonlake_pch_lp_community_1_groups[] = {
 452         &cannonlake_pch_lp_group_d,
 453         &cannonlake_pch_lp_group_f,
 454         &cannonlake_pch_lp_group_h,
 455         &cannonlake_pch_lp_group_vgpio,
 456 };
 457 const struct gpio_community cannonlake_pch_lp_community_1 = {
 458         .name           = "------- GPIO Community 1 -------",
 459         .pcr_port_id    = 0x6d,
 460         .group_count    = ARRAY_SIZE(cannonlake_pch_lp_community_1_groups),
 461         .groups         = cannonlake_pch_lp_community_1_groups,
 462 };
 463
 464 const struct gpio_group *const cannonlake_pch_lp_community_2_groups[] = {
 465         &cannonlake_pch_lp_group_gpd,
 466 };
 467
 468 const struct gpio_community cannonlake_pch_lp_community_2 = {
 469         .name           = "------- GPIO Community 2 -------",
 470         .pcr_port_id    = 0x6c,
 471         .group_count    = ARRAY_SIZE(cannonlake_pch_lp_community_2_groups),
 472         .groups         = cannonlake_pch_lp_community_2_groups,
 473 };
 474
 475 const struct gpio_group *const cannonlake_pch_lp_community_3_groups[] = {
 476         &cannonlake_pch_lp_group_aza,
 477         &cannonlake_pch_lp_group_cpu,
 478 };
 479
 480 const struct gpio_community cannonlake_pch_lp_community_3 = {
 481         .name           = "------- GPIO Community 3 -------",
 482         .pcr_port_id    = 0x6b,
 483         .group_count    = ARRAY_SIZE(cannonlake_pch_lp_community_3_groups),
 484         .groups         = cannonlake_pch_lp_community_3_groups,
 485 };
 486
 487 const struct gpio_group *const cannonlake_pch_lp_community_4_groups[] = {
 488         &cannonlake_pch_lp_group_c,
 489         &cannonlake_pch_lp_group_e,
 490         &cannonlake_pch_lp_group_jtag,
 491         &cannonlake_pch_lp_group_hvmos,
 492 };
 493
 494 const struct gpio_community cannonlake_pch_lp_community_4 = {
 495         .name           = "------- GPIO Community 4 -------",
 496         .pcr_port_id    = 0x6a,
 497         .group_count    = ARRAY_SIZE(cannonlake_pch_lp_community_4_groups),
 498         .groups         = cannonlake_pch_lp_community_4_groups,
 499 };
 500
 501 const struct gpio_community *const cannonlake_pch_lp_communities[] = {
 502         &cannonlake_pch_lp_community_0,
 503         &cannonlake_pch_lp_community_1,
 504         &cannonlake_pch_lp_community_2,
 505         &cannonlake_pch_lp_community_3,
 506         &cannonlake_pch_lp_community_4,
 507 };
 508
 509 #endif