src/arch/riscv/fp_asm.S

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * This file define some function used to swap value between memory
   5  * and float register. This will be used in misaligned access exception
   6  * handling.
   7  */
   8
   9 #if defined(__riscv_flen)
  10 #if __riscv_flen >= 32
  11
  12         .text
  13
  14 /* void read_f32(int regnum, uint32_t* v)
  15  *    regnum : which register want to read
  16  *    v : address to hold bits info of reading
  17  */
  18         .align  1
  19         .globl read_f32
  20 read_f32:
  21         la      a2, .Lr32_t
  22         andi    a0, a0, 31
  23         slli    a0, a0, 1
  24         add     a0, a0, a2
  25         lbu     a0, 0(a0)
  26         add     a0, a0, a2
  27         jr      a0
  28         .align  2
  29 .Lr32_t:
  30         .half   .Lr32_f0  - .Lr32_t
  31         .half   .Lr32_f1  - .Lr32_t
  32         .half   .Lr32_f2  - .Lr32_t
  33         .half   .Lr32_f3  - .Lr32_t
  34         .half   .Lr32_f4  - .Lr32_t
  35         .half   .Lr32_f5  - .Lr32_t
  36         .half   .Lr32_f6  - .Lr32_t
  37         .half   .Lr32_f7  - .Lr32_t
  38         .half   .Lr32_f8  - .Lr32_t
  39         .half   .Lr32_f9  - .Lr32_t
  40         .half   .Lr32_f10 - .Lr32_t
  41         .half   .Lr32_f11 - .Lr32_t
  42         .half   .Lr32_f12 - .Lr32_t
  43         .half   .Lr32_f13 - .Lr32_t
  44         .half   .Lr32_f14 - .Lr32_t
  45         .half   .Lr32_f15 - .Lr32_t
  46         .half   .Lr32_f16 - .Lr32_t
  47         .half   .Lr32_f17 - .Lr32_t
  48         .half   .Lr32_f18 - .Lr32_t
  49         .half   .Lr32_f19 - .Lr32_t
  50         .half   .Lr32_f20 - .Lr32_t
  51         .half   .Lr32_f21 - .Lr32_t
  52         .half   .Lr32_f22 - .Lr32_t
  53         .half   .Lr32_f23 - .Lr32_t
  54         .half   .Lr32_f24 - .Lr32_t
  55         .half   .Lr32_f25 - .Lr32_t
  56         .half   .Lr32_f26 - .Lr32_t
  57         .half   .Lr32_f27 - .Lr32_t
  58         .half   .Lr32_f28 - .Lr32_t
  59         .half   .Lr32_f29 - .Lr32_t
  60         .half   .Lr32_f30 - .Lr32_t
  61         .half   .Lr32_f31 - .Lr32_t
  62 #define  read32(which)  .Lr32_##which: fsw which, 0(a1); ret
  63         read32(f0)
  64         read32(f1)
  65         read32(f2)
  66         read32(f3)
  67         read32(f4)
  68         read32(f5)
  69         read32(f6)
  70         read32(f7)
  71         read32(f8)
  72         read32(f9)
  73         read32(f10)
  74         read32(f11)
  75         read32(f12)
  76         read32(f13)
  77         read32(f14)
  78         read32(f15)
  79         read32(f16)
  80         read32(f17)
  81         read32(f18)
  82         read32(f19)
  83         read32(f20)
  84         read32(f21)
  85         read32(f22)
  86         read32(f23)
  87         read32(f24)
  88         read32(f25)
  89         read32(f26)
  90         read32(f27)
  91         read32(f28)
  92         read32(f29)
  93         read32(f30)
  94         read32(f31)
  95
  96 /* void write_f32(int regnum, uint32_t* v)
  97  *    regnum: which register want to write
  98  *    v : address to hold bits info of writing
  99  */
 100         .align  1
 101         .globl write_f32
 102 write_f32:
 103         la      a2, .Lw32_t
 104         andi    a0, a0, 31
 105         slli    a0, a0, 1
 106         add     a0, a0, a2
 107         lbu     a0, 0(a0)
 108         add     a0, a0, a2
 109         jr      a0
 110         .align  2
 111 .Lw32_t:
 112         .half   .Lw32_f0  - .Lw32_t
 113         .half   .Lw32_f1  - .Lw32_t
 114         .half   .Lw32_f2  - .Lw32_t
 115         .half   .Lw32_f3  - .Lw32_t
 116         .half   .Lw32_f4  - .Lw32_t
 117         .half   .Lw32_f5  - .Lw32_t
 118         .half   .Lw32_f6  - .Lw32_t
 119         .half   .Lw32_f7  - .Lw32_t
 120         .half   .Lw32_f8  - .Lw32_t
 121         .half   .Lw32_f9  - .Lw32_t
 122         .half   .Lw32_f10 - .Lw32_t
 123         .half   .Lw32_f11 - .Lw32_t
 124         .half   .Lw32_f12 - .Lw32_t
 125         .half   .Lw32_f13 - .Lw32_t
 126         .half   .Lw32_f14 - .Lw32_t
 127         .half   .Lw32_f15 - .Lw32_t
 128         .half   .Lw32_f16 - .Lw32_t
 129         .half   .Lw32_f17 - .Lw32_t
 130         .half   .Lw32_f18 - .Lw32_t
 131         .half   .Lw32_f19 - .Lw32_t
 132         .half   .Lw32_f20 - .Lw32_t
 133         .half   .Lw32_f21 - .Lw32_t
 134         .half   .Lw32_f22 - .Lw32_t
 135         .half   .Lw32_f23 - .Lw32_t
 136         .half   .Lw32_f24 - .Lw32_t
 137         .half   .Lw32_f25 - .Lw32_t
 138         .half   .Lw32_f26 - .Lw32_t
 139         .half   .Lw32_f27 - .Lw32_t
 140         .half   .Lw32_f28 - .Lw32_t
 141         .half   .Lw32_f29 - .Lw32_t
 142         .half   .Lw32_f30 - .Lw32_t
 143         .half   .Lw32_f31 - .Lw32_t
 144 #define write32(which)  .Lw32_##which: flw which, 0(a1); ret
 145         write32(f0)
 146         write32(f1)
 147         write32(f2)
 148         write32(f3)
 149         write32(f4)
 150         write32(f5)
 151         write32(f6)
 152         write32(f7)
 153         write32(f8)
 154         write32(f9)
 155         write32(f10)
 156         write32(f11)
 157         write32(f12)
 158         write32(f13)
 159         write32(f14)
 160         write32(f15)
 161         write32(f16)
 162         write32(f17)
 163         write32(f18)
 164         write32(f19)
 165         write32(f20)
 166         write32(f21)
 167         write32(f22)
 168         write32(f23)
 169         write32(f24)
 170         write32(f25)
 171         write32(f26)
 172         write32(f27)
 173         write32(f28)
 174         write32(f29)
 175         write32(f30)
 176         write32(f31)
 177 #endif // __riscv_flen >= 32
 178
 179 #if __riscv_flen >= 64
 180
 181         .text
 182
 183 /* void read_f64(int regnum, uint64_t* v)
 184  *    regnum : which register want to read
 185  *    v : address to hold bits info of reading
 186  */
 187         .align  1
 188         .globl read_f64
 189 read_f64:
 190         la      a2, .Lr64_t
 191         andi    a0, a0, 31
 192         slli    a0, a0, 1
 193         add     a0, a0, a2
 194         lbu     a0, 0(a0)
 195         add     a0, a0, a2
 196         jr      a0
 197         .align  2
 198 .Lr64_t:
 199         .half   .Lr64_f0  - .Lr64_t
 200         .half   .Lr64_f1  - .Lr64_t
 201         .half   .Lr64_f2  - .Lr64_t
 202         .half   .Lr64_f3  - .Lr64_t
 203         .half   .Lr64_f4  - .Lr64_t
 204         .half   .Lr64_f5  - .Lr64_t
 205         .half   .Lr64_f6  - .Lr64_t
 206         .half   .Lr64_f7  - .Lr64_t
 207         .half   .Lr64_f8  - .Lr64_t
 208         .half   .Lr64_f9  - .Lr64_t
 209         .half   .Lr64_f10 - .Lr64_t
 210         .half   .Lr64_f11 - .Lr64_t
 211         .half   .Lr64_f12 - .Lr64_t
 212         .half   .Lr64_f13 - .Lr64_t
 213         .half   .Lr64_f14 - .Lr64_t
 214         .half   .Lr64_f15 - .Lr64_t
 215         .half   .Lr64_f16 - .Lr64_t
 216         .half   .Lr64_f17 - .Lr64_t
 217         .half   .Lr64_f18 - .Lr64_t
 218         .half   .Lr64_f19 - .Lr64_t
 219         .half   .Lr64_f20 - .Lr64_t
 220         .half   .Lr64_f21 - .Lr64_t
 221         .half   .Lr64_f22 - .Lr64_t
 222         .half   .Lr64_f23 - .Lr64_t
 223         .half   .Lr64_f24 - .Lr64_t
 224         .half   .Lr64_f25 - .Lr64_t
 225         .half   .Lr64_f26 - .Lr64_t
 226         .half   .Lr64_f27 - .Lr64_t
 227         .half   .Lr64_f28 - .Lr64_t
 228         .half   .Lr64_f29 - .Lr64_t
 229         .half   .Lr64_f30 - .Lr64_t
 230         .half   .Lr64_f31 - .Lr64_t
 231 #define  read64(which)  .Lr64_##which: fsd which, 0(a1); ret
 232         read64(f0)
 233         read64(f1)
 234         read64(f2)
 235         read64(f3)
 236         read64(f4)
 237         read64(f5)
 238         read64(f6)
 239         read64(f7)
 240         read64(f8)
 241         read64(f9)
 242         read64(f10)
 243         read64(f11)
 244         read64(f12)
 245         read64(f13)
 246         read64(f14)
 247         read64(f15)
 248         read64(f16)
 249         read64(f17)
 250         read64(f18)
 251         read64(f19)
 252         read64(f20)
 253         read64(f21)
 254         read64(f22)
 255         read64(f23)
 256         read64(f24)
 257         read64(f25)
 258         read64(f26)
 259         read64(f27)
 260         read64(f28)
 261         read64(f29)
 262         read64(f30)
 263         read64(f31)
 264
 265 /* void write_f64(int regnum, uint64_t* v)
 266  *    regnum: which register want to write
 267  *    v : address to hold bits info of writing
 268  */
 269         .align  1
 270         .globl write_f64
 271 write_f64:
 272         la      a2, .Lw64_t
 273         andi    a0, a0, 31
 274         slli    a0, a0, 1
 275         add     a0, a0, a2
 276         lbu     a0, 0(a0)
 277         add     a0, a0, a2
 278         jr      a0
 279         .align  2
 280 .Lw64_t:
 281         .half   .Lw64_f0  - .Lw64_t
 282         .half   .Lw64_f1  - .Lw64_t
 283         .half   .Lw64_f2  - .Lw64_t
 284         .half   .Lw64_f3  - .Lw64_t
 285         .half   .Lw64_f4  - .Lw64_t
 286         .half   .Lw64_f5  - .Lw64_t
 287         .half   .Lw64_f6  - .Lw64_t
 288         .half   .Lw64_f7  - .Lw64_t
 289         .half   .Lw64_f8  - .Lw64_t
 290         .half   .Lw64_f9  - .Lw64_t
 291         .half   .Lw64_f10 - .Lw64_t
 292         .half   .Lw64_f11 - .Lw64_t
 293         .half   .Lw64_f12 - .Lw64_t
 294         .half   .Lw64_f13 - .Lw64_t
 295         .half   .Lw64_f14 - .Lw64_t
 296         .half   .Lw64_f15 - .Lw64_t
 297         .half   .Lw64_f16 - .Lw64_t
 298         .half   .Lw64_f17 - .Lw64_t
 299         .half   .Lw64_f18 - .Lw64_t
 300         .half   .Lw64_f19 - .Lw64_t
 301         .half   .Lw64_f20 - .Lw64_t
 302         .half   .Lw64_f21 - .Lw64_t
 303         .half   .Lw64_f22 - .Lw64_t
 304         .half   .Lw64_f23 - .Lw64_t
 305         .half   .Lw64_f24 - .Lw64_t
 306         .half   .Lw64_f25 - .Lw64_t
 307         .half   .Lw64_f26 - .Lw64_t
 308         .half   .Lw64_f27 - .Lw64_t
 309         .half   .Lw64_f28 - .Lw64_t
 310         .half   .Lw64_f29 - .Lw64_t
 311         .half   .Lw64_f30 - .Lw64_t
 312         .half   .Lw64_f31 - .Lw64_t
 313 #define write64(which)  .Lw64_##which: fld which, 0(a1); ret
 314         write64(f0)
 315         write64(f1)
 316         write64(f2)
 317         write64(f3)
 318         write64(f4)
 319         write64(f5)
 320         write64(f6)
 321         write64(f7)
 322         write64(f8)
 323         write64(f9)
 324         write64(f10)
 325         write64(f11)
 326         write64(f12)
 327         write64(f13)
 328         write64(f14)
 329         write64(f15)
 330         write64(f16)
 331         write64(f17)
 332         write64(f18)
 333         write64(f19)
 334         write64(f20)
 335         write64(f21)
 336         write64(f22)
 337         write64(f23)
 338         write64(f24)
 339         write64(f25)
 340         write64(f26)
 341         write64(f27)
 342         write64(f28)
 343         write64(f29)
 344         write64(f30)
 345         write64(f31)
 346
 347 #endif // __riscv_flen >= 64
 348
 349 #endif // defined(__riscv_flen)