1 ## SPDX
-License
-Identifier
: GPL
-2.0-or-later
3 chip northbridge
/intel
/sandybridge
4 register
"spd_addresses" = "{0x50, 0, 0x52, 0}"
6 device ref host_bridge on
end
7 device ref peg10 on
end
10 chip southbridge
/intel
/bd82x6x
11 register
"sata_port_map" = "0x33"
12 register
"spi_lvscc" = "0x2005"
13 register
"spi_uvscc" = "0x2005"
14 register
"usb_port_config" = "{
31 device ref mei1 on
end
32 device ref mei2 off
end
33 device ref me_ide_r off
end
34 device ref me_kt off
end
35 device ref gbe off
end
36 device ref ehci2 on
end
39 device ref pcie_rp1 off
end
40 device ref pcie_rp2 off
end
41 device ref pcie_rp3 off
end
42 device ref pcie_rp4 off
end
43 device ref pcie_rp5 off
end
44 device ref pcie_rp6 off
end
45 device ref pcie_rp7 off
end
46 device ref pcie_rp8 off
end
48 device ref ehci1 on
end
49 device ref pci_bridge off
end
51 device ref sata1 on
end # SATA
(AHCI
)
52 device ref smbus on
end
53 device ref sata2 off
end # SATA
(Legacy
)
54 device ref thermal off
end