1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef __MAINBOARD_EMU_Q35_H__
4 #define __MAINBOARD_EMU_Q35_H__
6 #include <device/pci_type.h>
9 #define HOST_BRIDGE PCI_DEV(0, 0, 0)
11 #define EXT_TSEG_MBYTES 0x50
12 #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
14 #define D0F0_PCIEXBAR_LO 0x60
15 #define D0F0_PCIEXBAR_HI 0x64
17 #define D0F0_PAM(x) (0x90 + (x)) /* 0-6 */
20 #define G_SMRAME (1 << 3)
21 #define D_LCK (1 << 4)
22 #define D_CLS (1 << 5)
23 #define D_OPEN (1 << 6)
27 #define TSEG_SZ_MASK (3 << 1)
28 #define H_SMRAME (1 << 7)
30 uint32_t make_pciexbar(void);
32 void mainboard_machine_check(void);