src/mainboard/system76/gaze15/devicetree.cb

   1 # SPDX-License-Identifier: GPL-2.0-only
   2
   3 chip soc/intel/cannonlake
   4         register "common_soc_config" = "{
   5                 // Touchpad I2C bus
   6                 .i2c[0] = {
   7                         .speed = I2C_SPEED_FAST,
   8                         .rise_time_ns = 80,
   9                         .fall_time_ns = 110,
  10                 },
  11         }"
  12
  13 # CPU (soc/intel/cannonlake/cpu.c)
  14         # Power limit
  15         register "power_limits_config" = "{
  16                 .tdp_pl1_override = 45,
  17                 .tdp_pl2_override = 90,
  18         }"
  19
  20         # Enable Enhanced Intel SpeedStep
  21         register "eist_enable" = "true"
  22
  23 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
  24         register "enable_c6dram" = "1"
  25
  26 # FSP Silicon (soc/intel/cannonlake/fsp_params.c)
  27         # Misc
  28         register "AcousticNoiseMitigation" = "1"
  29
  30         # Power
  31         register "PchPmSlpS3MinAssert" = "3" # 50ms
  32         register "PchPmSlpS4MinAssert" = "1" # 1s
  33         register "PchPmSlpSusMinAssert" = "4" # 4s
  34         register "PchPmSlpAMinAssert" = "4" # 2s
  35
  36         # Thermal
  37         register "tcc_offset" = "8"
  38
  39         # Serial IRQ Continuous
  40         register "serirq_mode" = "SERIRQ_CONTINUOUS"
  41
  42 # PM Util (soc/intel/cannonlake/pmutil.c)
  43         # GPE configuration
  44         # Note that GPE events called out in ASL code rely on this
  45         # route. i.e. If this route changes then the affected GPE
  46         # offset bits also need to be changed.
  47         register "gpe0_dw0" = "PMC_GPP_K"
  48         register "gpe0_dw1" = "PMC_GPP_G"
  49         register "gpe0_dw2" = "PMC_GPP_E"
  50
  51 # Actual device tree
  52         device domain 0 on
  53                 device ref peg0         on
  54                         # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
  55                         register "PcieClkSrcUsage[8]" = "0x40"
  56                         register "PcieClkSrcClkReq[8]" = "8"
  57                 end
  58                 device ref igpu         on
  59                         register "gfx" = "GMA_DEFAULT_PANEL(0)"
  60                 end
  61                 device ref dptf         on
  62                         register "Device4Enable" = "1"
  63                 end
  64                 device ref thermal      on      end
  65                 device ref xhci         on
  66                         register "usb2_ports" = "{
  67                                 [0] = USB2_PORT_MID(OC_SKIP),           /* USB 3 Right */
  68                                 [1] = USB2_PORT_MID(OC_SKIP),           /* USB 3 Left */
  69                                 [2] = USB2_PORT_TYPE_C(OC_SKIP),        /* Type-C */
  70                                 [5] = USB2_PORT_MID(OC_SKIP),           /* USB 2 Left */
  71                                 [7] = USB2_PORT_MID(OC_SKIP),           /* Camera */
  72                                 [9] = USB2_PORT_MID(OC_SKIP),           /* Fingerprint */
  73                                 [13] = USB2_PORT_MID(OC_SKIP),          /* Bluetooth */
  74                         }"
  75                         register "usb3_ports" = "{
  76                                 [0] = USB3_PORT_DEFAULT(OC_SKIP),       /* USB 3 Right */
  77                                 [1] = USB3_PORT_DEFAULT(OC_SKIP),       /* USB 3 Left */
  78                                 [2] = USB3_PORT_DEFAULT(OC_SKIP),       /* Type-C */
  79                                 [3] = USB3_PORT_DEFAULT(OC_SKIP),       /* Type-C */
  80                         }"
  81                 end
  82                 device ref shared_sram  on      end
  83                 device ref cnvi_wifi    on
  84                         chip drivers/wifi/generic
  85                                 register "wake" = "GPE0_PME_B0"
  86                                 device generic 0 on end
  87                         end
  88                 end
  89                 device ref i2c1         on      end
  90                 device ref sata         on
  91                         register "SataPortsEnable" = "{
  92                                 [1] = 1, /* SSD (SATA1A) */
  93                                 [4] = 1, /* HDD (SATA4) */
  94                         }"
  95                 end
  96                 device ref uart2        on      end
  97                 device ref pcie_rp21    on
  98                         # PCI Express root port #21 x4, Clock 11 (SSD2)
  99                         register "PcieRpEnable[20]" = "1"
 100                         register "PcieRpLtrEnable[20]" = "1"
 101                         register "PcieClkSrcUsage[11]" = "20"
 102                         register "PcieClkSrcClkReq[11]" = "11"
 103                         register "PcieRpSlotImplemented[20]" = "1"
 104                 end
 105                 device ref pcie_rp9     on
 106                         # PCI Express root port #9 x4, Clock 10 (SSD)
 107                         register "PcieRpEnable[8]" = "1"
 108                         register "PcieRpLtrEnable[8]" = "1"
 109                         register "PcieClkSrcUsage[10]" = "8"
 110                         register "PcieClkSrcClkReq[10]" = "10"
 111                         register "PcieRpSlotImplemented[8]" = "1"
 112                 end
 113                 device ref pcie_rp14    on
 114                         # PCI Express root port #14 x1, Clock 6 (WLAN)
 115                         register "PcieRpEnable[13]" = "1"
 116                         register "PcieRpLtrEnable[13]" = "1"
 117                         register "PcieClkSrcUsage[6]" = "13"
 118                         register "PcieClkSrcClkReq[6]" = "6"
 119                         register "PcieRpSlotImplemented[13]" = "1"
 120                 end
 121                 device ref pcie_rp15    on
 122                         # PCI Express root port #15 x1, Clock 5 (LAN)
 123                         register "PcieRpEnable[14]" = "1"
 124                         register "PcieRpLtrEnable[14]" = "1"
 125                         register "PcieClkSrcUsage[5]" = "14"
 126                         register "PcieClkSrcClkReq[5]" = "5"
 127                         register "PcieRpSlotImplemented[14]" = "1"
 128                 end
 129                 device ref lpc_espi     on
 130                         register "gen1_dec" = "0x00040069"
 131                         register "gen2_dec" = "0x00fc0e01"
 132                         register "gen3_dec" = "0x00fc0f01"
 133                         chip drivers/pc80/tpm
 134                                 device pnp 0c31.0 on end
 135                         end
 136                 end
 137                 device ref hda          on
 138                         register "PchHdaAudioLinkHda" = "1"
 139                         register "PchHdaAudioLinkDmic0" = "1"
 140                         register "PchHdaAudioLinkDmic1" = "1"
 141                 end
 142                 device ref smbus        on      end
 143         end
 144 end