src/northbridge/intel/x4x/memmap.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #define __SIMPLE_DEVICE__
   4
   5 #include <cbmem.h>
   6 #include <commonlib/helpers.h>
   7 #include <arch/romstage.h>
   8 #include <device/pci_ops.h>
   9 #include <device/pci_def.h>
  10 #include <console/console.h>
  11 #include <cpu/x86/mtrr.h>
  12 #include <cpu/x86/smm.h>
  13 #include <northbridge/intel/x4x/x4x.h>
  14 #include <program_loading.h>
  15 #include <cpu/intel/smm_reloc.h>
  16 #include <types.h>
  17
  18 /** Decodes used Graphics Mode Select (GMS) to kilobytes. */
  19 u32 decode_igd_memory_size(const u32 gms)
  20 {
  21         static const u16 ggc2uma[] = {0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, 160, 224, 352};
  22
  23         if (gms >= ARRAY_SIZE(ggc2uma))
  24                 die("Bad Graphics Mode Select (GMS) setting.\n");
  25
  26         return ggc2uma[gms] << 10;
  27 }
  28
  29 /** Decodes used GTT Graphics Memory Size (GGMS) to kilobytes. */
  30 u32 decode_igd_gtt_size(const u32 gsm)
  31 {
  32         static const u8 ggc2gtt[] = {0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4};
  33
  34         if (gsm >= ARRAY_SIZE(ggc2gtt))
  35                 die("Bad GTT Graphics Memory Size (GGMS) setting.\n");
  36
  37         return ggc2gtt[gsm] << 10;
  38 }
  39
  40 /** Decodes used TSEG size to bytes. */
  41 u32 decode_tseg_size(const u32 esmramc)
  42 {
  43         if (!(esmramc & 1))
  44                 return 0;
  45
  46         switch ((esmramc >> 1) & 3) {
  47         case 0:
  48                 return 1 << 20;
  49         case 1:
  50                 return 2 << 20;
  51         case 2:
  52                 return 8 << 20;
  53         case 3:
  54         default:
  55                 die("Bad TSEG setting.\n");
  56         }
  57 }
  58
  59 static size_t northbridge_get_tseg_size(void)
  60 {
  61         const u8 esmramc = pci_read_config8(HOST_BRIDGE, D0F0_ESMRAMC);
  62         return decode_tseg_size(esmramc);
  63 }
  64
  65 static uintptr_t northbridge_get_tseg_base(void)
  66 {
  67         return pci_read_config32(HOST_BRIDGE, D0F0_TSEG);
  68 }
  69
  70 /* Depending of UMA and TSEG configuration, TSEG might start at any
  71  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  72  * CBMEM top downwards to 4 MiB boundary.
  73  */
  74 uintptr_t cbmem_top_chipset(void)
  75 {
  76         return ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
  77 }
  78
  79 void smm_region(uintptr_t *start, size_t *size)
  80 {
  81         *start = northbridge_get_tseg_base();
  82         *size = northbridge_get_tseg_size();
  83 }
  84
  85 void fill_postcar_frame(struct postcar_frame *pcf)
  86 {
  87         /* Cache 8 MiB region below the top of RAM and 2 MiB above top of
  88          * RAM to cover both cbmem as the TSEG region.
  89          */
  90         const uintptr_t top_of_ram = cbmem_top();
  91         postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
  92                         MTRR_TYPE_WRBACK);
  93         postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
  94                                northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
  95 }