src/soc/intel/alderlake/acpi/scs.asl

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <soc/pcr_ids.h>
   4
   5 #define PMCR_D0_MASK    0xFFFC
   6 #define PMCR_D3_MASK    0x0003
   7
   8 Scope (\_SB.PCI0) {
   9
  10         /*
  11          * Clear register 0x1C20/0x4820
  12          * Arg0 - PCR Port ID
  13          */
  14         Method(SCSC, 1, Serialized)
  15         {
  16                 PCRA (Arg0, 0x1C20, 0x0)
  17                 PCRA (Arg0, 0x4820, 0x0)
  18         }
  19
  20         /* EMMC */
  21         Device(EMMC) {
  22                 Name(_ADR, 0x001A0000)
  23                 Name (_DDN, "eMMC Controller")
  24                 Name(TEMP, 0)
  25
  26                 OperationRegion(SCSR, PCI_Config, 0x00, 0x100)
  27                 Field(SCSR, WordAcc, NoLock, Preserve) {
  28                         Offset (0x84),  /* PMECTRLSTATUS */
  29                         PMCR, 16,
  30                         Offset (0xA2),  /* PG_CONFIG */
  31                         , 2,
  32                         PGEN, 1,        /* PG_ENABLE */
  33                 }
  34
  35                 Method(_INI) {
  36                         /*
  37                          * Clear eMMC timeout registers. _PS0 is not called by kernel when
  38                          * boot source is not eMMC, but OS still initializes eMMC. So disable
  39                          * timeout registers when boot source is not eMMC. Ported from CB:25290.
  40                          */
  41                         SCSC (PID_EMMC)
  42                 }
  43
  44                 Method(_PS0, 0, Serialized) {
  45                         Stall (50)      /* Sleep 50 us */
  46
  47                         PGEN = 0        /* Disable PG */
  48
  49                         /* Clear register 0x1C20/0x4820 */
  50                         SCSC (PID_EMMC)
  51
  52                         /* Set Power State to D0 */
  53                         PMCR &= PMCR_D0_MASK
  54                         /* Additional config read to eMMC controller. Ported from CB:23312 */
  55                         TEMP = PMCR
  56                 }
  57
  58                 Method(_PS3, 0, Serialized) {
  59                         PGEN = 1        /* Enable PG */
  60
  61                         /* Set Power State to D3 */
  62                         PMCR |= PMCR_D3_MASK
  63                         /* Additional config read to eMMC controller. Ported from CB:23312 */
  64                         TEMP = PMCR
  65                 }
  66
  67                 Device (CARD)
  68                 {
  69                         Name (_ADR, 0x00000008)
  70                         Method (_RMV, 0, NotSerialized)
  71                         {
  72                                 Return (0)
  73                         }
  74                 }
  75         }
  76 }