src/soc/intel/alderlake/chip.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <device/pci.h>
   5 #include <fsp/api.h>
   6 #include <fsp/util.h>
   7 #include <gpio.h>
   8 #include <intelblocks/acpi.h>
   9 #include <intelblocks/cfg.h>
  10 #include <intelblocks/cse.h>
  11 #include <intelblocks/irq.h>
  12 #include <intelblocks/itss.h>
  13 #include <intelblocks/pcie_rp.h>
  14 #include <intelblocks/systemagent.h>
  15 #include <intelblocks/xdci.h>
  16 #include <soc/hsphy.h>
  17 #include <soc/intel/common/vbt.h>
  18 #include <soc/p2sb.h>
  19 #include <soc/pci_devs.h>
  20 #include <soc/pcie.h>
  21 #include <soc/ramstage.h>
  22 #include <soc/soc_chip.h>
  23
  24 #if CONFIG(HAVE_ACPI_TABLES)
  25 const char *soc_acpi_name(const struct device *dev)
  26 {
  27         if (dev->path.type == DEVICE_PATH_DOMAIN)
  28                 return "PCI0";
  29
  30         if (dev->path.type == DEVICE_PATH_USB) {
  31                 switch (dev->path.usb.port_type) {
  32                 case 0:
  33                         /* Root Hub */
  34                         return "RHUB";
  35                 case 2:
  36                         /* USB2 ports */
  37                         switch (dev->path.usb.port_id) {
  38                         case 0: return "HS01";
  39                         case 1: return "HS02";
  40                         case 2: return "HS03";
  41                         case 3: return "HS04";
  42                         case 4: return "HS05";
  43                         case 5: return "HS06";
  44                         case 6: return "HS07";
  45                         case 7: return "HS08";
  46                         case 8: return "HS09";
  47                         case 9: return "HS10";
  48                         case 10: return "HS11";
  49                         case 11: return "HS12";
  50                         case 12: return "HS13";
  51                         case 13: return "HS14";
  52                         }
  53                         break;
  54                 case 3:
  55                         /* USB3 ports */
  56                         switch (dev->path.usb.port_id) {
  57                         case 0: return "SS01";
  58                         case 1: return "SS02";
  59                         case 2: return "SS03";
  60                         case 3: return "SS04";
  61                         case 4: return "SS05";
  62                         case 5: return "SS06";
  63                         case 6: return "SS07";
  64                         case 7: return "SS08";
  65                         case 8: return "SS09";
  66                         case 9: return "SS10";
  67                         }
  68                         break;
  69                 }
  70                 return NULL;
  71         }
  72         if (dev->path.type != DEVICE_PATH_PCI)
  73                 return NULL;
  74
  75         switch (dev->path.pci.devfn) {
  76         case SA_DEVFN_ROOT:             return "MCHC";
  77 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
  78         case SA_DEVFN_CPU_PCIE1_0:      return "PEG1";
  79         case SA_DEVFN_CPU_PCIE1_1:      return "PEG2";
  80         case SA_DEVFN_CPU_PCIE6_0:      return "PEG0";
  81 #else
  82         case SA_DEVFN_CPU_PCIE1_0:      return "PEG2";
  83         case SA_DEVFN_CPU_PCIE6_0:      return "PEG0";
  84         case SA_DEVFN_CPU_PCIE6_2:      return "PEG1";
  85 #endif
  86         case SA_DEVFN_IGD:              return "GFX0";
  87         case SA_DEVFN_TCSS_XHCI:        return "TXHC";
  88         case SA_DEVFN_TCSS_XDCI:        return "TXDC";
  89         case SA_DEVFN_TCSS_DMA0:        return "TDM0";
  90         case SA_DEVFN_TCSS_DMA1:        return "TDM1";
  91         case SA_DEVFN_TBT0:             return "TRP0";
  92         case SA_DEVFN_TBT1:             return "TRP1";
  93         case SA_DEVFN_TBT2:             return "TRP2";
  94         case SA_DEVFN_TBT3:             return "TRP3";
  95         case SA_DEVFN_IPU:              return "IPU0";
  96         case SA_DEVFN_GNA:              return "GNA";
  97         case SA_DEVFN_DPTF:             return "TCPU";
  98         case PCH_DEVFN_ISH:             return "ISHB";
  99         case PCH_DEVFN_XHCI:            return "XHCI";
 100         case PCH_DEVFN_I2C0:            return "I2C0";
 101         case PCH_DEVFN_I2C1:            return "I2C1";
 102         case PCH_DEVFN_I2C2:            return "I2C2";
 103         case PCH_DEVFN_I2C3:            return "I2C3";
 104         case PCH_DEVFN_I2C4:            return "I2C4";
 105         case PCH_DEVFN_I2C5:            return "I2C5";
 106         case PCH_DEVFN_I2C6:            return "I2C6";
 107         case PCH_DEVFN_I2C7:            return "I2C7";
 108         case PCH_DEVFN_SATA:            return "SATA";
 109         case PCH_DEVFN_PCIE1:           return "RP01";
 110         case PCH_DEVFN_PCIE2:           return "RP02";
 111         case PCH_DEVFN_PCIE3:           return "RP03";
 112         case PCH_DEVFN_PCIE4:           return "RP04";
 113         case PCH_DEVFN_PCIE5:           return "RP05";
 114         case PCH_DEVFN_PCIE6:           return "RP06";
 115         case PCH_DEVFN_PCIE7:           return "RP07";
 116         case PCH_DEVFN_PCIE8:           return "RP08";
 117         case PCH_DEVFN_PCIE9:           return "RP09";
 118         case PCH_DEVFN_PCIE10:          return "RP10";
 119         case PCH_DEVFN_PCIE11:          return "RP11";
 120         case PCH_DEVFN_PCIE12:          return "RP12";
 121         case PCH_DEVFN_PCIE13:          return "RP13";
 122         case PCH_DEVFN_PCIE14:          return "RP14";
 123         case PCH_DEVFN_PCIE15:          return "RP15";
 124         case PCH_DEVFN_PCIE16:          return "RP16";
 125         case PCH_DEVFN_PCIE17:          return "RP17";
 126         case PCH_DEVFN_PCIE18:          return "RP18";
 127         case PCH_DEVFN_PCIE19:          return "RP19";
 128         case PCH_DEVFN_PCIE20:          return "RP20";
 129         case PCH_DEVFN_PCIE21:          return "RP21";
 130         case PCH_DEVFN_PCIE22:          return "RP22";
 131         case PCH_DEVFN_PCIE23:          return "RP23";
 132         case PCH_DEVFN_PCIE24:          return "RP24";
 133 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
 134         /* Avoid conflicts with PCH-N eMMC */
 135         case PCH_DEVFN_PCIE25:          return "RP25";
 136         case PCH_DEVFN_PCIE26:          return "RP26";
 137         case PCH_DEVFN_PCIE27:          return "RP27";
 138         case PCH_DEVFN_PCIE28:          return "RP28";
 139 #endif
 140         case PCH_DEVFN_PMC:             return "PMC";
 141         case PCH_DEVFN_UART0:           return "UAR0";
 142         case PCH_DEVFN_UART1:           return "UAR1";
 143         case PCH_DEVFN_UART2:           return "UAR2";
 144         case PCH_DEVFN_GSPI0:           return "SPI0";
 145         case PCH_DEVFN_GSPI1:           return "SPI1";
 146         case PCH_DEVFN_GSPI2:           return "SPI2";
 147         case PCH_DEVFN_GSPI3:           return "SPI3";
 148         /* Keeping ACPI device name coherent with ec.asl */
 149         case PCH_DEVFN_ESPI:            return "LPCB";
 150         case PCH_DEVFN_HDA:             return "HDAS";
 151         case PCH_DEVFN_SMBUS:           return "SBUS";
 152         case PCH_DEVFN_GBE:             return "GLAN";
 153         case PCH_DEVFN_SRAM:            return "SRAM";
 154         case PCH_DEVFN_SPI:             return "FSPI";
 155         case PCH_DEVFN_CSE:             return "HEC1";
 156 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
 157         case PCH_DEVFN_EMMC:            return "EMMC";
 158 #endif
 159         }
 160
 161         return NULL;
 162 }
 163 #endif
 164
 165 #if CONFIG(SOC_INTEL_STORE_ISH_FW_VERSION)
 166 /*
 167  * SoC override API to identify if ISH Firmware existed inside CSE FPT.
 168  *
 169  * Identifying the ISH enabled device is required to conclude that the ISH
 170  * partition also is available (because ISH may be default enabled for non-UFS
 171  * platforms as well starting with Alder Lake).
 172  */
 173 bool soc_is_ish_partition_enabled(void)
 174 {
 175         struct device *ish = pcidev_path_on_root(PCH_DEVFN_ISH);
 176         uint16_t ish_pci_id = ish ? pci_read_config16(ish, PCI_DEVICE_ID) : 0xFFFF;
 177
 178         if (ish_pci_id == 0xFFFF)
 179                 return false;
 180
 181         return true;
 182 }
 183 #endif
 184
 185 /* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */
 186 static void soc_fill_gpio_pm_configuration(void)
 187 {
 188         uint8_t value[TOTAL_GPIO_COMM];
 189         const config_t *config = config_of_soc();
 190
 191         if (config->gpio_override_pm)
 192                 memcpy(value, config->gpio_pm, sizeof(value));
 193         else
 194                 memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value));
 195
 196         gpio_pm_configure(value, TOTAL_GPIO_COMM);
 197 }
 198
 199 void soc_init_pre_device(void *chip_info)
 200 {
 201         /* HSPHY FW needs to be loaded before FSP silicon init */
 202         load_and_init_hsphy();
 203
 204         /* Perform silicon specific init. */
 205         fsp_silicon_init();
 206
 207          /* Display FIRMWARE_VERSION_INFO_HOB */
 208         fsp_display_fvi_version_hob();
 209
 210         soc_fill_gpio_pm_configuration();
 211
 212         /* Swap enabled PCI ports in device tree if needed. */
 213         pcie_rp_update_devicetree(get_pch_pcie_rp_table());
 214
 215         /* Swap enabled TBT root ports in device tree if needed. */
 216         pcie_rp_update_devicetree(get_tbt_pcie_rp_table());
 217
 218         /*
 219          * Earlier when coreboot used to send EOP at late as possible caused
 220          * issue of delayed response from CSE since CSE was busy loading payload.
 221          * To resolve the issue, EOP should be sent earlier than current sequence
 222          * in the boot sequence at BS_DEV_INIT.
 223          * Intel CSE team recommends to send EOP close to FW init (between FSP-S exit and
 224          * current boot sequence) to reduce message response time from CSE hence moving
 225          * sending EOP to earlier stage.
 226          */
 227         if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY) ||
 228             CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) {
 229                 printk(BIOS_INFO, "Sending EOP early from SoC\n");
 230                 cse_send_end_of_post();
 231         }
 232 }
 233
 234 static void cpu_fill_ssdt(const struct device *dev)
 235 {
 236         if (!generate_pin_irq_map())
 237                 printk(BIOS_ERR, "Failed to generate ACPI _PRT table!\n");
 238
 239         generate_cpu_entries(dev);
 240 }
 241
 242 static void cpu_set_north_irqs(struct device *dev)
 243 {
 244         irq_program_non_pch();
 245 }
 246
 247 static struct device_operations pci_domain_ops = {
 248         .read_resources   = &pci_domain_read_resources,
 249         .set_resources    = &pci_domain_set_resources,
 250         .scan_bus         = &pci_host_bridge_scan_bus,
 251 #if CONFIG(HAVE_ACPI_TABLES)
 252         .acpi_name        = &soc_acpi_name,
 253         .acpi_fill_ssdt   = ssdt_set_above_4g_pci,
 254 #endif
 255 };
 256
 257 static struct device_operations cpu_bus_ops = {
 258         .read_resources   = noop_read_resources,
 259         .set_resources    = noop_set_resources,
 260         .enable_resources = cpu_set_north_irqs,
 261 #if CONFIG(HAVE_ACPI_TABLES)
 262         .acpi_fill_ssdt   = cpu_fill_ssdt,
 263 #endif
 264 };
 265
 266 static void soc_enable(struct device *dev)
 267 {
 268         struct device_operations *soc_p2sb_ops = (struct device_operations *)&p2sb_ops;
 269         /*
 270          * Set the operations if it is a special bus type or a hidden PCI
 271          * device.
 272          */
 273         if (dev->path.type == DEVICE_PATH_DOMAIN)
 274                 dev->ops = &pci_domain_ops;
 275         else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
 276                 dev->ops = &cpu_bus_ops;
 277         else if (dev->path.type == DEVICE_PATH_PCI &&
 278                  dev->path.pci.devfn == PCH_DEVFN_PMC)
 279                 dev->ops = &pmc_ops;
 280         else if (dev->path.type == DEVICE_PATH_PCI &&
 281                  dev->path.pci.devfn == PCH_DEVFN_P2SB)
 282                 dev->ops = soc_p2sb_ops;
 283         else if (dev->path.type == DEVICE_PATH_GPIO)
 284                 block_gpio_enable(dev);
 285 }
 286
 287 struct chip_operations soc_intel_alderlake_ops = {
 288         .name = "Intel Alderlake",
 289         .enable_dev     = &soc_enable,
 290         .init           = &soc_init_pre_device,
 291 };