src/soc/intel/alderlake/systemagent.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * This file is created based on Intel Alder Lake Processor SA Datasheet
   5  * Document number: 619503
   6  * Chapter number: 3
   7  */
   8
   9 #include <arch/ioapic.h>
  10 #include <console/console.h>
  11 #include <cpu/x86/msr.h>
  12 #include <device/device.h>
  13 #include <device/pci.h>
  14 #include <intelblocks/cpulib.h>
  15 #include <intelblocks/msr.h>
  16 #include <intelblocks/power_limit.h>
  17 #include <intelblocks/systemagent.h>
  18 #include <soc/iomap.h>
  19 #include <soc/soc_chip.h>
  20 #include <soc/systemagent.h>
  21 #include <spi_flash.h>
  22 #include <stddef.h>
  23
  24 /*
  25  * SoC implementation
  26  *
  27  * Add all known fixed memory ranges for Host Controller/Memory
  28  * controller.
  29  */
  30 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
  31 {
  32         static const struct sa_mmio_descriptor soc_fixed_resources[] = {
  33                 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
  34                 { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
  35                 { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
  36                 { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
  37                 { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
  38
  39                 /* first field (sa_mmio_descriptor.index) is not used, setting to 0: */
  40                 { 0, CRAB_ABORT_BASE_ADDR, CRAB_ABORT_SIZE, "CRAB_ABORT" },
  41                 { 0, TPM_BASE_ADDRESS, TPM_SIZE, "TPM" },
  42                 { 0, LT_SECURITY_BASE_ADDR, LT_SECURITY_SIZE, "LT_SECURITY" },
  43                 { 0, IO_APIC_ADDR, APIC_SIZE, "APIC" },
  44                 // PCH_PRESERVERD covers:
  45                 // TraceHub SW BAR, SBREG, PMC MBAR, SPI BAR0, SerialIo BAR in ACPI mode
  46                 // eSPI LGMR BAR, eSPI2 SEGMR BAR, TraceHub MTB BAR, TraceHub FW BAR
  47                 // see fsp/ClientOneSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h
  48                 { 0, PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE, "PCH_RESERVED" },
  49         };
  50
  51         sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
  52                         ARRAY_SIZE(soc_fixed_resources));
  53
  54         /* Add Vt-d resources if VT-d is enabled */
  55         if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
  56                 return;
  57
  58         sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
  59                         ARRAY_SIZE(soc_vtd_resources));
  60 }
  61
  62 /*
  63  * set MMIO resource's fields
  64  */
  65 static void set_mmio_resource(
  66         struct sa_mmio_descriptor *resource,
  67         uint64_t base,
  68         uint64_t size,
  69         const char *description)
  70 {
  71         if (resource == NULL) {
  72                 printk(BIOS_ERR, "%s: argument resource is NULL for %s\n",
  73                 __func__, description);
  74                 return;
  75         }
  76         resource->base = base;
  77         resource->size = size;
  78         resource->description = description;
  79 }
  80
  81 int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base,
  82         uint64_t *prmrr_mask)
  83 {
  84         msr_t msr;
  85         msr = rdmsr(MSR_PRMRR_BASE_0);
  86         *prmrr_base = (uint64_t)msr.hi << 32 | msr.lo;
  87         msr = rdmsr(MSR_PRMRR_PHYS_MASK);
  88         *prmrr_mask = (uint64_t)msr.hi << 32 | msr.lo;
  89         return 0;
  90 }
  91
  92 /*
  93  * SoC implementation
  94  *
  95  * Add all known configurable memory ranges for Host Controller/Memory
  96  * controller.
  97  */
  98 void soc_add_configurable_mmio_resources(struct device *dev, int *resource_cnt)
  99 {
 100         uint64_t size, base, tseg_base;
 101         int count = 0;
 102         struct sa_mmio_descriptor cfg_rsrc[6]; /* Increase size when adding more resources */
 103
 104         /* MMCONF */
 105         size = sa_get_mmcfg_size();
 106         if (size > 0)
 107                 set_mmio_resource(&(cfg_rsrc[count++]), CONFIG_ECAM_MMCONF_BASE_ADDRESS,
 108                         size, "MMCONF");
 109
 110         /* DSM */
 111         size = sa_get_dsm_size();
 112         if (size > 0) {
 113                 base = pci_read_config32(dev, BDSM) & 0xFFF00000;
 114                 set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DSM");
 115         }
 116
 117         /* TSEG */
 118         size = sa_get_tseg_size();
 119         tseg_base = sa_get_tseg_base();
 120         if (size > 0)
 121                 set_mmio_resource(&(cfg_rsrc[count++]), tseg_base, size, "TSEG");
 122
 123         /* PMRR */
 124         size = get_valid_prmrr_size();
 125         if (size > 0) {
 126                 uint64_t mask;
 127                 if (soc_get_uncore_prmmr_base_and_mask(&base, &mask) == 0) {
 128                         base &= mask;
 129                         set_mmio_resource(&(cfg_rsrc[count++]), base, size, "PMRR");
 130                 } else {
 131                         printk(BIOS_ERR, "SA: Failed to get PRMRR base and mask\n");
 132                 }
 133         }
 134
 135         /* GSM */
 136         size = sa_get_gsm_size();
 137         if (size > 0) {
 138                 base = sa_get_gsm_base();
 139                 set_mmio_resource(&(cfg_rsrc[count++]), base, size, "GSM");
 140         }
 141
 142         /* DPR */
 143         size = sa_get_dpr_size();
 144         if (size > 0) {
 145                 /* DPR just below TSEG: */
 146                 base = tseg_base - size;
 147                 set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DPR");
 148         }
 149
 150         /* Add all the above */
 151         sa_add_fixed_mmio_resources(dev, resource_cnt, cfg_rsrc, count);
 152 }
 153
 154 /*
 155  * SoC implementation
 156  *
 157  * Perform System Agent Initialization during Ramstage phase.
 158  */
 159 void soc_systemagent_init(struct device *dev)
 160 {
 161         struct soc_power_limits_config *soc_config;
 162         struct device *sa;
 163         uint16_t sa_pci_id;
 164         u8 tdp;
 165         size_t i;
 166         config_t *config;
 167
 168         /* Enable Power Aware Interrupt Routing */
 169         enable_power_aware_intr();
 170
 171         config = config_of_soc();
 172
 173         /* Get System Agent PCI ID */
 174         sa = pcidev_path_on_root(SA_DEVFN_ROOT);
 175         sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF;
 176
 177         tdp = get_cpu_tdp();
 178
 179         /* Choose power limits configuration based on the CPU SA PCI ID and
 180          * CPU TDP value. */
 181         for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) {
 182                 if (sa_pci_id == cpuid_to_adl[i].cpu_id &&
 183                                 tdp == cpuid_to_adl[i].cpu_tdp) {
 184                         soc_config = &config->power_limits_config[cpuid_to_adl[i].limits];
 185                         set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
 186                         break;
 187                 }
 188         }
 189
 190         if (i == ARRAY_SIZE(cpuid_to_adl)) {
 191                 printk(BIOS_ERR, "unknown SA ID: 0x%4x, skipped power limits configuration.\n",
 192                         sa_pci_id);
 193                 return;
 194         }
 195 }
 196
 197 uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
 198 {
 199         switch (capid0_a_ddrsz) {
 200         case 1:
 201                 return 8192;
 202         case 2:
 203                 return 4096;
 204         case 3:
 205                 return 2048;
 206         default:
 207                 return 65536;
 208         }
 209 }