src/soc/intel/apollolake/acpi/scs.asl

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 Scope (\_SB.PCI0) {
   4         /* 0xD6- is the port address */
   5         /* 0x600- is the dynamic clock gating control register offset (GENR) */
   6         OperationRegion (SBMM, SystemMemory,
   7                 CONFIG_PCR_BASE_ADDRESS | (0xD6 << PCR_PORTID_SHIFT) | 0x0600, 0x18)
   8         Field (SBMM, DWordAcc, NoLock, Preserve)
   9         {
  10                 GENR, 32,
  11                 Offset (0x08),
  12                 ,  5, /* bit[5] represents Force Card Detect SD Card */
  13                 GRR3,  1, /* GPPRVRW3 for SD Card detect Bypass. It's active high */
  14         }
  15
  16         /* SCC power gate control method, this method must be serialized as
  17          * multiple device will control the GENR register
  18          *
  19          * Arguments: (2)
  20          * Arg0: 0-AND  1-OR
  21          * Arg1: Value
  22          */
  23         Method (SCPG, 2, Serialized)
  24         {
  25                 if (Arg0 == 1) {
  26                         ^GENR |= Arg1
  27                 } ElseIf (Arg0 == 0) {
  28                         ^GENR &= Arg1
  29                 }
  30         }
  31
  32         /* eMMC */
  33         Device (SDHA) {
  34                 Name (_ADR, 0x001C0000)
  35                 Name (_DDN, "Intel(R) eMMC Controller - 80865ACC")
  36                 Name (UUID, ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D"))
  37
  38                 /*
  39                  * Device Specific Method
  40                  * Arg0 - UUID
  41                  * Arg1 - Revision
  42                  * Arg2 - Function Index
  43                  */
  44                 Method (_DSM, 4)
  45                 {
  46                         If (Arg0 == ^UUID) {
  47                                 /*
  48                                  * Function 9: Device Readiness Durations
  49                                  * Returns a package of five integers covering
  50                                  * various device related delays in PCIe Base Spec.
  51                                  */
  52                                 If (Arg2 == 9) {
  53                                         /*
  54                                          * Function 9 support for revision 3.
  55                                          * ECN link for function definitions
  56                                          * [https://pcisig.com/sites/default/files/
  57                                          * specification_documents/
  58                                          * ECN_fw_latency_optimization_final.pdf]
  59                                          */
  60                                         If (Arg1 == 3) {
  61                                                 /*
  62                                                  * Integer 0: FW reset time.
  63                                                  * Integer 1: FW data link up time.
  64                                                  * Integer 2: FW functional level reset
  65                                                  * time.
  66                                                  * Integer 3: FW D3 hot to D0 time.
  67                                                  * Integer 4: FW VF enable time.
  68                                                  * set ACPI constant Ones for elements
  69                                                  * where overriding the default value
  70                                                  * is not desired.
  71                                                  */
  72                                                 Return (Package (5) {0, Ones, Ones,
  73                                                                             Ones, Ones})
  74                                         }
  75                                 }
  76                         }
  77                         Return (Buffer() { 0x00 })
  78                 }
  79
  80                 Method (_PS0, 0, NotSerialized)
  81                 {
  82                         /* Clear clock gate
  83                          * Clear bit 6 and 0
  84                          */
  85                         ^^SCPG(0,0xFFFFFFBE)
  86                         /* Sleep 2 ms */
  87                         Sleep (2)
  88                 }
  89
  90                 Method (_PS3, 0, NotSerialized)
  91                 {
  92                         /* Enable power gate
  93                          * Restore clock gate
  94                          * Restore bit 6 and 0
  95                          */
  96                         ^^SCPG(1,0x00000041)
  97                 }
  98
  99                 Device (CARD)
 100                 {
 101                         Name (_ADR, 0x00000008)
 102                         Method (_RMV, 0, NotSerialized)
 103                         {
 104                                 Return (0)
 105                         }
 106                 }
 107         } /* Device (SDHA) */
 108
 109         /* SD CARD */
 110         Device (SDCD)
 111         {
 112                 Name (_ADR, 0x001B0000)
 113                 Name (_S0W, 4) /* _S0W: S0 Device Wake State */
 114                 Name (SCD0, 0) /* Store SD_CD DW0 address */
 115
 116                 /* Set the host ownership of sdcard cd during kernel boot */
 117                 Method (_INI, 0)
 118                 {
 119                         /* Check SDCard CD port is valid */
 120                         If (\SCDP != 0 && \SCDO != 0)
 121                         {
 122                                 /* Store DW0 address of SD_CD */
 123                                 SCD0 = GDW0 (\SCDP, \SCDO)
 124                                 /* Get the current SD_CD ownership */
 125                                 Local0 = \_SB.GHO (\SCDP, \SCDO)
 126                                 /* Set host ownership as GPIO in HOSTSW_OWN reg */
 127                                 Local0 |= 1 << (\SCDO % 32)
 128                                 \_SB.SHO (\SCDP, \SCDO, Local0)
 129                         }
 130                 }
 131
 132                 Method (_PS0, 0, NotSerialized)
 133                 {
 134                         /* Check SDCard CD port is valid */
 135                         If (\SCDP != 0 && \SCDO != 0)
 136                         {
 137                                 /* Store DW0 into local0 to get rxstate of GPIO */
 138                                 Local0 = \_SB.GPC0 (SCD0)
 139                                 /* Extract rxstate [bit 1] of sdcard card detect pin */
 140                                 Local0 &= PAD_CFG0_RX_STATE
 141                                 /* If the sdcard is present, rxstate is low.
 142                                  * If sdcard is not present, rxstate is High.
 143                                  * Write the inverted value of rxstate to GRR3.
 144                                  */
 145                                 If (Local0 == 0) {
 146                                         ^^GRR3 = 1
 147                                 } Else {
 148                                         ^^GRR3 = 0
 149                                 }
 150                                 Sleep (2)
 151                         }
 152                 }
 153
 154                 Method (_PS3, 0, NotSerialized)
 155                 {
 156                         /* Clear GRR3 to Power Gate SD Controller */
 157                         ^^GRR3 = 0
 158                 }
 159
 160                 Device (CARD)
 161                 {
 162                         Name (_ADR, 0x00000008)
 163                         Method (_RMV, 0, NotSerialized)
 164                         {
 165                                 Return (1)
 166                         }
 167                 }
 168         } /* Device (SDCD) */
 169 }