src/soc/intel/apollolake/gpio_glk.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <gpio.h>
   4 #include <intelblocks/pcr.h>
   5 #include <soc/pcr_ids.h>
   6 #include <soc/pm.h>
   7
   8 static const struct reset_mapping rst_map[] = {
   9         { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
  10         { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
  11         { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
  12 };
  13
  14 static const struct pad_group glk_community_audio_groups[] = {
  15         INTEL_GPP(AUDIO_OFFSET, AUDIO_OFFSET, GPIO_175),        /* AUDIO 0 */
  16 };
  17
  18 static const struct pad_group glk_community_nw_groups[] = {
  19         INTEL_GPP(NW_OFFSET, NW_OFFSET, GPIO_31),       /* NORTHWEST 0 */
  20         INTEL_GPP(NW_OFFSET, GPIO_32, GPIO_63),         /* NORTHWEST 1 */
  21         INTEL_GPP(NW_OFFSET, GPIO_64, GPIO_214),        /* NORTHWEST 2 */
  22 };
  23
  24 static const struct pad_group glk_community_scc_groups[] = {
  25         INTEL_GPP(SCC_OFFSET, SCC_OFFSET, GPIO_206),    /* SCC 0 */
  26         INTEL_GPP(SCC_OFFSET, GPIO_207, GPIO_209),      /* SCC 1 */
  27 };
  28
  29 static const struct pad_group glk_community_n_groups[] = {
  30         INTEL_GPP(N_OFFSET, N_OFFSET, GPIO_107),        /* NORTH 0 */
  31         INTEL_GPP(N_OFFSET, GPIO_108, GPIO_139),        /* NORTH 1 */
  32         INTEL_GPP(N_OFFSET, GPIO_140, GPIO_155),        /* NORTH 2 */
  33 };
  34
  35 static const struct pad_community glk_gpio_communities[] = {
  36         {
  37                 .port = PID_GPIO_NW,
  38                 .first_pad = NW_OFFSET,
  39                 .last_pad = GPIO_214,
  40                 .num_gpi_regs = NUM_NW_GPI_REGS,
  41                 .gpi_status_offset = 0,
  42                 .pad_cfg_base = PAD_CFG_BASE,
  43                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
  44                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
  45                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
  46                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
  47                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
  48                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
  49                 .name = "GPIO_NORTHWEST",
  50                 .acpi_path = "\\_SB.GPO0",
  51                 .reset_map = rst_map,
  52                 .num_reset_vals = ARRAY_SIZE(rst_map),
  53                 .groups = glk_community_nw_groups,
  54                 .num_groups = ARRAY_SIZE(glk_community_nw_groups),
  55         }, {
  56                 .port = PID_GPIO_N,
  57                 .first_pad = N_OFFSET,
  58                 .last_pad = GPIO_155,
  59                 .num_gpi_regs = NUM_N_GPI_REGS,
  60                 .gpi_status_offset = NUM_NW_GPI_REGS,
  61                 .pad_cfg_base = PAD_CFG_BASE,
  62                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
  63                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
  64                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
  65                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
  66                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
  67                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
  68                 .name = "GPIO_NORTH",
  69                 .acpi_path = "\\_SB.GPO1",
  70                 .reset_map = rst_map,
  71                 .num_reset_vals = ARRAY_SIZE(rst_map),
  72                 .groups = glk_community_n_groups,
  73                 .num_groups = ARRAY_SIZE(glk_community_n_groups),
  74         }, {
  75                 .port = PID_GPIO_AUDIO,
  76                 .first_pad = AUDIO_OFFSET,
  77                 .last_pad = GPIO_175,
  78                 .num_gpi_regs = NUM_AUDIO_GPI_REGS,
  79                 .gpi_status_offset = NUM_NW_GPI_REGS + NUM_N_GPI_REGS,
  80                 .pad_cfg_base = PAD_CFG_BASE,
  81                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
  82                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
  83                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
  84                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
  85                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
  86                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
  87                 .name = "GPIO_AUDIO",
  88                 .acpi_path = "\\_SB.GPO2",
  89                 .reset_map = rst_map,
  90                 .num_reset_vals = ARRAY_SIZE(rst_map),
  91                 .groups = glk_community_audio_groups,
  92                 .num_groups = ARRAY_SIZE(glk_community_audio_groups),
  93         }, {
  94                 .port = PID_GPIO_SCC,
  95                 .first_pad = SCC_OFFSET,
  96                 .last_pad = GPIO_209,
  97                 .num_gpi_regs = NUM_SCC_GPI_REGS,
  98                 .gpi_status_offset = NUM_NW_GPI_REGS + NUM_N_GPI_REGS +
  99                         NUM_AUDIO_GPI_REGS,
 100                 .pad_cfg_base = PAD_CFG_BASE,
 101                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 102                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 103                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 104                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 105                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 106                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 107                 .name = "GPIO_SCC",
 108                 .acpi_path = "\\_SB.GPO3",
 109                 .reset_map = rst_map,
 110                 .num_reset_vals = ARRAY_SIZE(rst_map),
 111                 .groups = glk_community_scc_groups,
 112                 .num_groups = ARRAY_SIZE(glk_community_scc_groups),
 113         },
 114 };
 115
 116 const struct pad_community *soc_gpio_get_community(size_t *num_communities)
 117 {
 118         *num_communities = ARRAY_SIZE(glk_gpio_communities);
 119         return glk_gpio_communities;
 120 }
 121
 122 const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
 123 {
 124         static const struct pmc_to_gpio_route routes[] = {
 125                 { PMC_GPE_SCC_31_0, GPIO_GPE_SCC_31_0 },
 126                 { PMC_GPE_SCC_63_32, GPIO_GPE_SCC_63_32 },
 127                 { PMC_GPE_NW_31_0, GPIO_GPE_NW_31_0 },
 128                 { PMC_GPE_NW_63_32, GPIO_GPE_NW_63_32 },
 129                 { PMC_GPE_NW_95_64, GPIO_GPE_NW_95_64 },
 130                 /*
 131                  * PMC_GPE_NW_127_96 maps to GPIO group 3, which is reserved and
 132                  * cannot be set in GPE0_DWx. Hence, it is skipped here.
 133                  */
 134                 { PMC_GPE_N_31_0, GPIO_GPE_N_31_0 },
 135                 { PMC_GPE_N_63_32, GPIO_GPE_N_63_32 },
 136                 { PMC_GPE_N_95_64, GPIO_GPE_N_95_64 },
 137                 { PMC_GPE_AUDIO_31_0, GPIO_GPE_AUDIO_31_0 },
 138         };
 139         *num = ARRAY_SIZE(routes);
 140         return routes;
 141 }