src/soc/intel/braswell/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/io.h>
   4 #include <console/console.h>
   5 #include <device/mmio.h>
   6 #include <device/pci.h>
   7 #include <gpio.h>
   8 #include <soc/pm.h>
   9 #include <soc/smm.h>
  10
  11 #define GPIO_DEBUG
  12
  13 /* gpio map to pad number LUTs */
  14
  15 static const u8 gpncommunity_gpio_to_pad[GP_NORTH_COUNT] = {
  16          0,  1,  2,  3,  4,  5,  6,  7,  8, 15,
  17         16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
  18         26, 27, 30, 31, 32, 33, 34, 35, 36, 37,
  19         38, 39, 40, 41, 45, 46, 47, 48, 49, 50,
  20         51, 52, 53, 54, 55, 56, 60, 61, 62, 63,
  21         64, 65, 66, 67, 68, 69, 70, 71, 72 };
  22
  23 static const u8 gpsecommunity_gpio_to_pad[GP_SOUTHEAST_COUNT] = {
  24          0,  1,  2,  3,  4,  5,  6,  7, 15, 16,
  25         17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
  26         30, 31, 32, 33, 34, 35, 45, 46, 47, 48,
  27         49, 50, 51, 52, 60, 61, 62, 63, 64, 65,
  28         66, 67, 68, 69, 75, 76, 77, 78, 79, 80,
  29         81, 82, 83, 84, 85 };
  30
  31 static const u8 gpswcommunity_gpio_to_pad[GP_SOUTHWEST_COUNT] = {
  32          0,  1,  2,  3,  4,  5,  6,  7, 15, 16,
  33         17, 18, 19, 20, 21, 22, 30, 31, 32, 33,
  34         34, 35, 36, 37, 45, 46, 47, 48, 49, 50,
  35         51, 52, 60, 61, 62, 63, 64, 65, 66, 67,
  36         75, 76, 77, 78, 79, 80, 81, 82, 90, 91,
  37         92, 93, 94, 95, 96, 97 };
  38
  39 static const u8 gpecommunity_gpio_to_pad[GP_EAST_COUNT] = {
  40          0,  1,  2,  3,  4,  5,  6,  7,  8,  9,
  41         10, 11, 15, 16, 17, 18, 19, 20, 21, 22,
  42         23, 24, 25, 26 };
  43
  44 /* GPIO Community descriptions */
  45 static const struct gpio_bank gpnorth_community = {
  46         .gpio_count  = GP_NORTH_COUNT,
  47         .gpio_to_pad = gpncommunity_gpio_to_pad,
  48         .pad_base    = COMMUNITY_GPNORTH_BASE,
  49         .has_gpe_en  = GPE_CAPABLE,
  50         .has_wake_en = 1,
  51 };
  52
  53 static const struct gpio_bank gpsoutheast_community = {
  54         .gpio_count  = GP_SOUTHEAST_COUNT,
  55         .gpio_to_pad = gpsecommunity_gpio_to_pad,
  56         .pad_base    = COMMUNITY_GPSOUTHEAST_BASE,
  57         .has_gpe_en  = GPE_CAPABLE_NONE,
  58         .has_wake_en = 1,
  59 };
  60
  61 static const struct gpio_bank gpsouthwest_community = {
  62         .gpio_count  = GP_SOUTHWEST_COUNT,
  63         .gpio_to_pad = gpswcommunity_gpio_to_pad,
  64         .pad_base    = COMMUNITY_GPSOUTHWEST_BASE,
  65         .has_gpe_en  = GPE_CAPABLE,
  66         .has_wake_en = 1,
  67 };
  68
  69 static const struct gpio_bank gpeast_community = {
  70         .gpio_count  = GP_EAST_COUNT,
  71         .gpio_to_pad = gpecommunity_gpio_to_pad,
  72         .pad_base    = COMMUNITY_GPEAST_BASE,
  73         .has_gpe_en  = GPE_CAPABLE_NONE,
  74         .has_wake_en = 1,
  75 };
  76
  77 static void setup_gpio_route(const struct soc_gpio_map *sw_gpios,
  78                              const struct soc_gpio_map *n_gpios)
  79 {
  80         const struct soc_gpio_map *n_config;
  81         const struct soc_gpio_map *sw_config;
  82         uint32_t route_reg = 0;
  83         uint32_t int_selection = 0;
  84         uint32_t alt_gpio_smi = 0;
  85         uint32_t gpe0a_en = 0;
  86         int gpio = 0;
  87         int north_done = 0;
  88         int south_done = 0;
  89
  90         for (sw_config = sw_gpios, n_config = n_gpios;
  91                 (!north_done || !south_done); sw_config++, n_config++, gpio++) {
  92                 /* When north config is done */
  93                 if ((gpio > GP_NORTH_COUNT) || (n_config->pad_conf0 == GPIO_LIST_END))
  94                         north_done = 1;
  95
  96                 /* When southwest config is done */
  97                 if ((gpio > GP_SOUTHWEST_COUNT) || (sw_config->pad_conf0 == GPIO_LIST_END))
  98                         south_done = 1;
  99
 100                 /* Route north gpios */
 101                 if (!north_done) {
 102                          /* Int select from 8 to 15 */
 103                         int_selection = ((n_config->pad_conf0 >> 28) & 0xf);
 104
 105                         if (n_config->gpe == SMI) {
 106                                 /* Set the corresponding bits (01) as per the interrupt line */
 107                                 route_reg |= (1 << ((int_selection - 8) * 2));
 108
 109                                 /* Reset the higher bit */
 110                                 route_reg    &= ~(1 << ((int_selection - 8) * 2 + 1));
 111                                 alt_gpio_smi |=  (1 <<  (int_selection + 8));
 112
 113                         } else if (n_config->gpe == SCI) {
 114                                 /* Set the corresponding bits as per the interrupt line */
 115                                 route_reg |= (1 << (((int_selection - 8) * 2) + 1));
 116
 117                                 /* Reset the bit */
 118                                 route_reg &= ~(1 << ((int_selection - 8) * 2));
 119                                 gpe0a_en  |=  (1 <<  (int_selection + 8));
 120                         }
 121                 }
 122
 123                 /* Route southwest gpios */
 124                 if (!south_done) {
 125                          /* Int select from 8 to 15 */
 126                         int_selection = ((sw_config->pad_conf0 >> 28) & 0xf);
 127
 128                         if (sw_config->gpe == SMI) {
 129                                 /* Set the corresponding bits (10) as per the interrupt line */
 130                                 route_reg    |=  (1 << (int_selection * 2));
 131                                 route_reg    &= ~(1 << (int_selection * 2 + 1));
 132                                 alt_gpio_smi |=  (1 << (int_selection + 16));
 133
 134                         } else if (sw_config->gpe == SCI) {
 135                                 /* Set the corresponding bits as per the interrupt line */
 136                                 route_reg |= (1 << ((int_selection * 2) + 1));
 137
 138                                 /* Reset the bit */
 139                                 route_reg &= ~(1 << (int_selection * 2));
 140                                 gpe0a_en  |=  (1 << (int_selection + 16));
 141                         }
 142                 }
 143         }
 144
 145         /* Enable gpe bits in GPE0A_EN_REG */
 146         outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0A_EN_REG);
 147
 148 #ifdef GPIO_DEBUG
 149         printk(BIOS_DEBUG, "gpio_rout = %x alt_gpio_smi = %x  gpe0a_en = %x\n",
 150         route_reg, alt_gpio_smi, gpe0a_en);
 151 #endif
 152         /* Save as an SMM param */
 153         smm_southcluster_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg);
 154 }
 155
 156 static void setup_gpios(const struct soc_gpio_map *gpios, const struct gpio_bank *community)
 157 {
 158         const struct soc_gpio_map *config;
 159         int gpio = 0;
 160         u32 reg, family, internal_pad_num;
 161         u32 mmio_addr, int_selection;
 162         u32 gpio_wake0 = 0;
 163         u32 gpio_wake1 = 0;
 164         u32 gpio_int_mask = 0;
 165
 166         if (!gpios)
 167                 return;
 168
 169         for (config = gpios; config->pad_conf0 != GPIO_LIST_END; config++, gpio++) {
 170                 if (gpio > community->gpio_count)
 171                         break;
 172
 173                 /* Pad configuration registers */
 174                 family = community->gpio_to_pad[gpio] / MAX_FAMILY_PAD_GPIO_NO;
 175                 internal_pad_num = community->gpio_to_pad[gpio] % MAX_FAMILY_PAD_GPIO_NO;
 176
 177                 /*
 178                  * Calculate the MMIO Address for GPIO pin control register pointed by index.
 179                  * REG = IOBASE + COMMUNITY_BASE + 0x4400 + (0x400 * FAMILY_NUM) + (8 * PAD_NUM)
 180                  */
 181                 mmio_addr = FAMILY_PAD_REGS_OFF + (FAMILY_PAD_REGS_SIZE * family) +
 182                                 (GPIO_REGS_SIZE * internal_pad_num);
 183
 184                 reg = community->pad_base + mmio_addr;
 185
 186                 /* Get int selection value */
 187                 int_selection = ((config->pad_conf0 >> 28) & 0xf);
 188
 189                 /* Get int mask register value */
 190                 gpio_int_mask |= (config->int_mask << int_selection);
 191
 192                 /* Wake capable programming, some communities have 2 wake regs */
 193                 if (gpio > 31)
 194                         gpio_wake1 |= config->wake_mask << (gpio % 32);
 195                 else
 196                         gpio_wake0 |= config->wake_mask << gpio;
 197
 198                 if (!config->skip_config) {
 199 #ifdef GPIO_DEBUG
 200                         printk(BIOS_DEBUG,
 201                                 "Write Pad: Base(%x) - conf0 = %x conf1= %x gpio #- %d pad # = %d\n",
 202                                 reg, config->pad_conf0, config->pad_conf1,
 203                                 community->gpio_to_pad[gpio], gpio);
 204 #endif
 205                         /* Write pad configurations to conf0 and conf1 register */
 206                         write32((void *)(reg + PAD_CONF0_REG), config->pad_conf0);
 207                         write32((void *)(reg + PAD_CONF1_REG), config->pad_conf1);
 208                 }
 209         }
 210
 211 #ifdef GPIO_DEBUG
 212         printk(BIOS_DEBUG, "gpio_wake_mask0 = %x gpio_wake_mask1 = %x gpio_int_mask = %x\n",
 213                 gpio_wake0, gpio_wake1, gpio_int_mask);
 214 #endif
 215
 216         /* Wake */
 217         write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG0), gpio_wake0);
 218
 219         /* Wake mask config for communities with 2 regs */
 220         if (community->gpio_count > 32)
 221                 write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG1), gpio_wake1);
 222
 223         /* Interrupt */
 224         write32((void *)(community->pad_base + GPIO_INTERRUPT_MASK), gpio_int_mask);
 225 }
 226
 227 void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap)
 228 {
 229         if (config) {
 230                 /*
 231                  * Write the default value 0xffffff to the SW write_access_policy_interrupt_reg
 232                  * to allow the SW interrupt mask register to be set
 233                  */
 234                 write32((void *)(COMMUNITY_GPSOUTHWEST_BASE + 0x108), 0xffffffff);
 235
 236                 printk(BIOS_DEBUG, "north\n");
 237                 setup_gpios(config->north, &gpnorth_community);
 238
 239                 printk(BIOS_DEBUG, "southwest\n");
 240                 setup_gpios(config->southwest, &gpsouthwest_community);
 241
 242                 printk(BIOS_DEBUG, "southeast\n");
 243                 setup_gpios(config->southeast, &gpsoutheast_community);
 244
 245                 printk(BIOS_DEBUG, "east\n");
 246                 setup_gpios(config->east, &gpeast_community);
 247
 248                 printk(BIOS_DEBUG, "Routing SW and N gpios\n");
 249                 setup_gpio_route(config->southwest, config->north);
 250         }
 251
 252         /*
 253          * Set on die termination feature with pull up value
 254          * and drive the pad high for TAP_TDO and TAP_TMS
 255          */
 256         if (!enable_xdp_tap)
 257                 printk(BIOS_DEBUG, "Tri-state TDO and TMS\n");
 258 }
 259
 260 __weak struct soc_gpio_config *mainboard_get_gpios(void)
 261 {
 262         printk(BIOS_DEBUG, "Default/empty GPIO config\n");
 263         return NULL;
 264 }