src/soc/intel/cannonlake/cpu.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/pci.h>
   5 #include <cpu/x86/mp.h>
   6 #include <cpu/x86/msr.h>
   7 #include <cpu/intel/smm_reloc.h>
   8 #include <cpu/intel/turbo.h>
   9 #include <intelblocks/cpulib.h>
  10 #include <intelblocks/mp_init.h>
  11 #include <soc/cpu.h>
  12 #include <soc/msr.h>
  13 #include <soc/pci_devs.h>
  14 #include <soc/systemagent.h>
  15 #include <cpu/x86/mtrr.h>
  16 #include <cpu/intel/microcode.h>
  17 #include <cpu/intel/common/common.h>
  18 #include <types.h>
  19
  20 #include "chip.h"
  21
  22 bool cpu_soc_is_in_untrusted_mode(void)
  23 {
  24         msr_t msr;
  25
  26         msr = rdmsr(MSR_BIOS_DONE);
  27         return !!(msr.lo & ENABLE_IA_UNTRUSTED);
  28 }
  29
  30 void cpu_soc_bios_done(void)
  31 {
  32         msr_t msr;
  33
  34         msr = rdmsr(MSR_BIOS_DONE);
  35         msr.lo |= ENABLE_IA_UNTRUSTED;
  36         wrmsr(MSR_BIOS_DONE, msr);
  37 }
  38
  39 static void soc_fsp_load(void)
  40 {
  41         fsps_load();
  42 }
  43
  44 static void configure_misc(void)
  45 {
  46         msr_t msr;
  47
  48         config_t *conf = config_of_soc();
  49
  50         msr = rdmsr(IA32_MISC_ENABLE);
  51         msr.lo |= (1 << 0);     /* Fast String enable */
  52         msr.lo |= (1 << 3);     /* TM1/TM2/EMTTM enable */
  53         wrmsr(IA32_MISC_ENABLE, msr);
  54
  55         /* Set EIST status */
  56         cpu_set_eist(conf->eist_enable);
  57
  58         /* Disable Thermal interrupts */
  59         msr.lo = 0;
  60         msr.hi = 0;
  61         wrmsr(IA32_THERM_INTERRUPT, msr);
  62
  63         /* Enable package critical interrupt only */
  64         msr.lo = 1 << 4;
  65         msr.hi = 0;
  66         wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
  67
  68         /* Enable PROCHOT */
  69         msr = rdmsr(MSR_POWER_CTL);
  70         msr.lo |= (1 << 0);     /* Enable Bi-directional PROCHOT as an input */
  71         msr.lo |= (1 << 18);    /* Enable Energy/Performance Bias control */
  72         msr.lo |= (1 << 23);    /* Lock it */
  73         wrmsr(MSR_POWER_CTL, msr);
  74 }
  75
  76 static void configure_c_states(const config_t *const cfg)
  77 {
  78         msr_t msr;
  79
  80         msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
  81         if (cfg->max_package_c_state && (msr.lo & 0xf) >= cfg->max_package_c_state) {
  82                 msr.lo = (msr.lo & ~0xf) | ((cfg->max_package_c_state - 1) & 0xf);
  83         }
  84         msr.lo |= CST_CFG_LOCK_MASK;
  85         wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
  86
  87         /* C-state Interrupt Response Latency Control 0 - package C3 latency */
  88         msr.hi = 0;
  89         msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
  90         wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr);
  91
  92         /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */
  93         msr.hi = 0;
  94         msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
  95         wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr);
  96
  97         /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */
  98         msr.hi = 0;
  99         msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
 100         wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr);
 101
 102         /* C-state Interrupt Response Latency Control 3 - package C8 */
 103         msr.hi = 0;
 104         msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT;
 105         wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
 106
 107         /* C-state Interrupt Response Latency Control 4 - package C9 */
 108         msr.hi = 0;
 109         msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT;
 110         wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
 111
 112         /* C-state Interrupt Response Latency Control 5 - package C10 */
 113         msr.hi = 0;
 114         msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT;
 115         wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
 116 }
 117
 118 /* All CPUs including BSP will run the following function. */
 119 void soc_core_init(struct device *cpu)
 120 {
 121         config_t *cfg = config_of_soc();
 122
 123         /* Clear out pending MCEs */
 124         /* TODO(adurbin): This should only be done on a cold boot. Also, some
 125          * of these banks are core vs package scope. For now every CPU clears
 126          * every bank. */
 127         mca_configure();
 128
 129         enable_lapic_tpr();
 130
 131         /* Configure c-state interrupt response time */
 132         configure_c_states(cfg);
 133
 134         /* Configure Enhanced SpeedStep and Thermal Sensors */
 135         configure_misc();
 136
 137         set_aesni_lock();
 138
 139         enable_pm_timer_emulation();
 140
 141         /* Enable Direct Cache Access */
 142         configure_dca_cap();
 143
 144         /* Set energy policy */
 145         set_energy_perf_bias(ENERGY_POLICY_NORMAL);
 146
 147         if (cfg->cpu_turbo_disable)
 148                 disable_turbo();
 149         else
 150                 enable_turbo();
 151
 152         /* Enable Vmx */
 153         set_feature_ctrl_vmx_arg(CONFIG(ENABLE_VMX) && !cfg->disable_vmx);
 154         set_feature_ctrl_lock();
 155 }
 156
 157 static void per_cpu_smm_trigger(void)
 158 {
 159         /* Relocate the SMM handler. */
 160         smm_relocate();
 161 }
 162
 163 void smm_lock(void)
 164 {
 165         /*
 166          * LOCK the SMM memory window and enable normal SMM.
 167          * After running this function, only a full reset can
 168          * make the SMM registers writable again. D_LCK bit
 169          * requires the PCI 0xcf8/0xcfc I/O access.
 170          */
 171         printk(BIOS_DEBUG, "Locking SMM.\n");
 172         pci_io_write_config8(SA_DEVFN_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
 173 }
 174
 175 static void post_mp_init(void)
 176 {
 177         /* Set Max Ratio */
 178         cpu_set_max_ratio();
 179
 180         /*
 181          * Now that all APs have been relocated as well as the BSP let SMIs
 182          * start flowing.
 183          */
 184         global_smi_enable_no_pwrbtn();
 185
 186         /* Lock down the SMRAM space. */
 187         smm_lock();
 188 }
 189
 190 static const struct mp_ops mp_ops = {
 191         /*
 192          * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,
 193          * that are set prior to ramstage.
 194          * Real MTRRs programming are being done after resource allocation.
 195          */
 196         .pre_mp_init = soc_fsp_load,
 197         .get_cpu_count = get_cpu_count,
 198         .get_smm_info = smm_info,
 199         .get_microcode_info = get_microcode_info,
 200         .pre_mp_smm_init = smm_initialize,
 201         .per_cpu_smm_trigger = per_cpu_smm_trigger,
 202         .relocation_handler = smm_relocation_handler,
 203         .post_mp_init = post_mp_init,
 204 };
 205
 206 void mp_init_cpus(struct bus *cpu_bus)
 207 {
 208         /* TODO: Handle mp_init_with_smm failure? */
 209         mp_init_with_smm(cpu_bus, &mp_ops);
 210
 211         /* Thermal throttle activation offset */
 212         configure_tcc_thermal_target();
 213 }
 214
 215 int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
 216 {
 217         msr_t msr1;
 218         msr_t msr2;
 219
 220         /*
 221          * If PRMRR/SGX is supported the FIT microcode load will set the msr
 222          * 0x08b with the Patch revision id one less than the id in the
 223          * microcode binary. The PRMRR support is indicated in the MSR
 224          * MTRRCAP[12]. If SGX is not enabled, check and avoid reloading the
 225          * same microcode during CPU initialization. If SGX is enabled, as
 226          * part of SGX BIOS initialization steps, the same microcode needs to
 227          * be reloaded after the core PRMRR MSRs are programmed.
 228          */
 229         msr1 = rdmsr(MTRR_CAP_MSR);
 230         msr2 = rdmsr(MSR_PRMRR_PHYS_BASE);
 231         if (msr2.lo && (current_patch_id == new_patch_id - 1))
 232                 return 0;
 233
 234         return (msr1.lo & MTRR_CAP_PRMRR) &&
 235                 (current_patch_id == new_patch_id - 1);
 236 }