src/soc/intel/cannonlake/elog.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #define __SIMPLE_DEVICE__
   4
   5 #include <bootstate.h>
   6 #include <console/console.h>
   7 #include <device/pci_ops.h>
   8 #include <stdint.h>
   9 #include <elog.h>
  10 #include <intelblocks/pmclib.h>
  11 #include <intelblocks/xhci.h>
  12 #include <soc/pci_devs.h>
  13 #include <soc/pm.h>
  14
  15 struct pme_status_info {
  16         pci_devfn_t dev;
  17         uint8_t reg_offset;
  18         uint32_t elog_event;
  19 };
  20
  21 #define PME_STS_BIT             (1 << 15)
  22
  23 static void pch_log_pme_internal_wake_source(void)
  24 {
  25         size_t i;
  26         pci_devfn_t dev;
  27         uint16_t val;
  28         bool dev_found = false;
  29
  30         const struct pme_status_info pme_status_info[] = {
  31                 { PCH_DEV_HDA, 0x54, ELOG_WAKE_SOURCE_PME_HDA },
  32                 { PCH_DEV_GBE, 0xcc, ELOG_WAKE_SOURCE_PME_GBE },
  33                 { PCH_DEV_SATA, 0x74, ELOG_WAKE_SOURCE_PME_SATA },
  34                 { PCH_DEV_CSE, 0x54, ELOG_WAKE_SOURCE_PME_CSE },
  35                 { PCH_DEV_USBOTG, 0x84, ELOG_WAKE_SOURCE_PME_XDCI },
  36                 /*
  37                  * The power management control/status register is not
  38                  * listed in the cannonlake PCH EDS. We have been told
  39                  * that the PMCS register is at offset 0xCC.
  40                  */
  41                 { PCH_DEV_CNViWIFI, 0xcc, ELOG_WAKE_SOURCE_PME_WIFI },
  42         };
  43         const struct xhci_wake_info xhci_wake_info[] = {
  44                 { PCH_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI },
  45         };
  46
  47         for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) {
  48                 dev = pme_status_info[i].dev;
  49                 if (!dev)
  50                         continue;
  51
  52                 val = pci_read_config16(dev, pme_status_info[i].reg_offset);
  53
  54                 if ((val == 0xFFFF) || !(val & PME_STS_BIT))
  55                         continue;
  56
  57                 elog_add_event_wake(pme_status_info[i].elog_event, 0);
  58                 dev_found = true;
  59         }
  60
  61         /*
  62          * Check the XHCI controllers' USB2 & USB3 ports for wake events. There
  63          * are cases (GSMI logging for S0ix clears PME_STS_BIT) where the XHCI
  64          * controller's PME_STS_BIT may have already been cleared, so the host
  65          * controller wake wouldn't get logged here; therefore, the host
  66          * controller wake event is logged before its corresponding port wake
  67          * event is logged.
  68          */
  69         dev_found |= xhci_update_wake_event(xhci_wake_info,
  70                                             ARRAY_SIZE(xhci_wake_info));
  71
  72         if (!dev_found)
  73                 elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
  74 }
  75
  76 static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
  77 {
  78         int i;
  79
  80         gpe0_sts &= gpe0_en;
  81
  82         for (i = 0; i <= 31; i++) {
  83                 if (gpe0_sts & (1 << i))
  84                         elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start);
  85         }
  86 }
  87
  88 static void pch_log_wake_source(const struct chipset_power_state *ps)
  89 {
  90         /* Power Button */
  91         if (ps->pm1_sts & PWRBTN_STS)
  92                 elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
  93
  94         /* RTC */
  95         if (ps->pm1_sts & RTC_STS)
  96                 elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
  97
  98         /* PCI Express (TODO: determine wake device) */
  99         if (ps->pm1_sts & PCIEXPWAK_STS)
 100                 elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
 101
 102         /* PME (TODO: determine wake device) */
 103         if (ps->gpe0_sts[GPE_STD] & PME_STS)
 104                 elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
 105
 106         /* XHCI - "Power Management Event Bus 0" events include XHCI */
 107         if (ps->gpe0_sts[GPE_STD] & PME_B0_STS)
 108                 pch_log_pme_internal_wake_source();
 109
 110         /* SMBUS Wake */
 111         if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS)
 112                 elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
 113
 114         /* Log GPIO events in set 1-3 */
 115         pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0);
 116         pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32);
 117         pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64);
 118         /* Treat the STD as an extension of GPIO to obtain visibility. */
 119         pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96);
 120 }
 121
 122 static void pch_log_power_and_resets(const struct chipset_power_state *ps)
 123 {
 124         /* Thermal Trip */
 125         if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP)
 126                 elog_add_event(ELOG_TYPE_THERM_TRIP);
 127
 128         /* PWR_FLR Power Failure */
 129         if (ps->gen_pmcon_a & PWR_FLR)
 130                 elog_add_event(ELOG_TYPE_POWER_FAIL);
 131
 132         /* SUS Well Power Failure */
 133         if (ps->gen_pmcon_a & SUS_PWR_FLR)
 134                 elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
 135
 136         /* TCO Timeout */
 137         if (ps->prev_sleep_state != ACPI_S3 &&
 138             ps->tco2_sts & TCO2_STS_SECOND_TO)
 139                 elog_add_event(ELOG_TYPE_TCO_RESET);
 140
 141         /* Power Button Override */
 142         if (ps->pm1_sts & PRBTNOR_STS)
 143                 elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
 144
 145         /* RTC reset */
 146         if (ps->gen_pmcon_b & RTC_BATTERY_DEAD)
 147                 elog_add_event(ELOG_TYPE_RTC_RESET);
 148
 149         /* Host Reset Status */
 150         if (ps->gen_pmcon_a & HOST_RST_STS)
 151                 elog_add_event(ELOG_TYPE_SYSTEM_RESET);
 152
 153         /* ACPI Wake Event */
 154         if (ps->prev_sleep_state != ACPI_S0)
 155                 elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state);
 156 }
 157
 158 static void pch_log_state(void *unused)
 159 {
 160         struct chipset_power_state *ps = pmc_get_power_state();
 161
 162         if (!ps) {
 163                 printk(BIOS_ERR, "chipset_power_state not found!\n");
 164                 return;
 165         }
 166
 167         /* Power and Reset */
 168         pch_log_power_and_resets(ps);
 169
 170         /* Wake Sources */
 171         if (ps->prev_sleep_state > ACPI_S0)
 172                 pch_log_wake_source(ps);
 173 }
 174
 175 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, pch_log_state, NULL);
 176
 177 void elog_gsmi_cb_platform_log_wake_source(void)
 178 {
 179         struct chipset_power_state ps;
 180         pmc_fill_pm_reg_info(&ps);
 181         pch_log_wake_source(&ps);
 182 }