src/soc/intel/cannonlake/pmc.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootstate.h>
   4 #include <console/console.h>
   5 #include <device/mmio.h>
   6 #include <device/device.h>
   7 #include <intelblocks/acpi.h>
   8 #include <intelblocks/pmc.h>
   9 #include <intelblocks/pmclib.h>
  10 #include <intelblocks/rtc.h>
  11 #include <soc/pci_devs.h>
  12 #include <soc/pm.h>
  13
  14 #include "chip.h"
  15
  16 static void pm1_enable_pwrbtn_smi(void *unused)
  17 {
  18         /*
  19          * Enable power button SMI only before jumping to payload. This ensures
  20          * that:
  21          * 1. Power button SMI is enabled only after coreboot is done.
  22          * 2. On resume path, power button SMI is not enabled and thus avoids
  23          * any shutdowns because of power button presses due to power button
  24          * press in resume path.
  25          */
  26         pmc_update_pm1_enable(PWRBTN_EN);
  27 }
  28
  29 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
  30
  31 static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)
  32 {
  33         uint32_t reg;
  34         uint8_t *pmcbase = pmc_mmio_regs();
  35
  36         printk(BIOS_DEBUG, "%sabling Deep S%c\n",
  37                 enable ? "En" : "Dis", sx + '0');
  38         reg = read32(pmcbase + offset);
  39         if (enable)
  40                 reg |= mask;
  41         else
  42                 reg &= ~mask;
  43         write32(pmcbase + offset, reg);
  44 }
  45
  46 static void config_deep_s5(int on_ac, int on_dc)
  47 {
  48         /* Treat S4 the same as S5. */
  49         config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac);
  50         config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc);
  51         config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac);
  52         config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc);
  53 }
  54
  55 static void config_deep_s3(int on_ac, int on_dc)
  56 {
  57         config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac);
  58         config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc);
  59 }
  60
  61 static void config_deep_sx(uint32_t deepsx_config)
  62 {
  63         uint32_t reg;
  64         uint8_t *pmcbase = pmc_mmio_regs();
  65
  66         reg = read32(pmcbase + DSX_CFG);
  67         reg &= ~DSX_CFG_MASK;
  68         reg |= deepsx_config;
  69         write32(pmcbase + DSX_CFG, reg);
  70 }
  71
  72 static void soc_pmc_read_resources(struct device *dev)
  73 {
  74         struct resource *res;
  75
  76         /* Add the fixed MMIO resource */
  77         mmio_range(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE);
  78
  79         /* Add the fixed I/O resource */
  80         res = new_resource(dev, 1);
  81         res->base = (resource_t)ACPI_BASE_ADDRESS;
  82         res->size = (resource_t)ACPI_BASE_SIZE;
  83         res->limit = res->base + res->size - 1;
  84         res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  85 }
  86
  87 static void soc_pmc_enable(struct device *dev)
  88 {
  89         const config_t *config = config_of_soc();
  90
  91         rtc_init();
  92
  93         pmc_set_power_failure_state(true);
  94         pmc_gpe_init();
  95
  96         config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
  97         config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
  98         config_deep_sx(config->deep_sx_config);
  99 }
 100
 101 static void soc_pmc_init(struct device *dev)
 102 {
 103         /*
 104          * PMC initialization happens earlier for this SoC because FSP-Silicon
 105          * init hides PMC from PCI bus. However, pmc_set_acpi_mode, which
 106          * disables ACPI mode doesn't need to happen that early and can be
 107          * delayed till typical BS_DEV_INIT. This ensures that ACPI mode
 108          * disabling happens the same way for all SoCs and hence the ordering of
 109          * events is the same.
 110          *
 111          * This is important to ensure that the ordering does not break the
 112          * assumptions of any other drivers (e.g. ChromeEC) which could be
 113          * taking different actions based on disabling of ACPI (e.g. flushing of
 114          * all EC hostevent bits).
 115          *
 116          * Because the device is set as `hidden` in the devicetree, enumeration
 117          * is skipped, but the device callbacks are still called as if it were
 118          * found.
 119          */
 120         pmc_set_acpi_mode();
 121
 122         /*
 123          * Disable ACPI PM timer based on Kconfig
 124          *
 125          * Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
 126          * Disabling ACPI PM timer also switches off TCO.
 127          */
 128         if (!CONFIG(USE_PM_ACPI_TIMER))
 129                 setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
 130 }
 131
 132 static void pmc_fill_ssdt(const struct device *dev)
 133 {
 134         if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP))
 135                 generate_acpi_power_engine();
 136 }
 137
 138 /*
 139  * `pmc_final` function is native implementation of equivalent events performed by
 140  * each FSP NotifyPhase() API invocations.
 141  *
 142  *
 143  * Clear PMCON status bits (Global Reset/Power Failure/Host Reset Status bits)
 144  *
 145  * Perform the PMCON status bit clear operation from `.final`
 146  * to cover any such chances where later boot stage requested a global
 147  * reset and PMCON status bit remains set.
 148  */
 149 static void pmc_final(struct device *dev)
 150 {
 151         pmc_clear_pmcon_sts();
 152 }
 153
 154 struct device_operations pmc_ops = {
 155         .read_resources   = soc_pmc_read_resources,
 156         .set_resources    = noop_set_resources,
 157         .init             = soc_pmc_init,
 158         .enable           = soc_pmc_enable,
 159 #if CONFIG(HAVE_ACPI_TABLES)
 160         .acpi_fill_ssdt   = pmc_fill_ssdt,
 161 #endif
 162         .scan_bus         = scan_static_bus,
 163         .final            = pmc_final,
 164 };